azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<vup>
gatecat: do you have any guidance on how quick the prjtrellis fuzzers are roughtly? (specifically 051-pio_ioconfig)
<gatecat>
that one can take a few hours iirc
<gatecat>
you can set the TRELLIS_JOBS env var to something higher than the default of 4 if you have plenty of cores and RAM
<vup>
I tried that, but it doesn't seem to really help
<gatecat>
ah that fuzzer might not support the parallelism
<azonenberg>
cr1901: she's a brilliant physicist and generally smart person, but also has a bit of a god complex
<azonenberg>
a shame the first black woman to get a PhD from MIT had to be such an asshole lol
<gatecat>
vup: I suspect this was a regression from the move from boost::python to pybind11
<vup>
hmm yeah, just `python3 -c 'import pytrellis; pytrellis.EnumSettingBits()'` also triggers it
<azonenberg>
She had everything she needed to make RPI a great place to be a student
<azonenberg>
then she went dictator instead
<cr1901>
azonenberg: Yes indeed. And almost certainly ppl use that as a shield an excuse to shit on an accomplished black woman just because she's an accomplished black woman. As opposed to "she pissed a lot of ppl off"
<vup>
gatecat: Ok I think I know how to fix this, but I there there are a bunch more constructors missing. Is there a easier way to test this than just running all the fuzzers?
<gatecat>
vup: unfortunately, probably not, but if it looks reasonable then it's probably OK in this case
<vup>
well I was more looking for a way to check all the fuzzer actually work after that
<gatecat>
at least seeing if they start is probably a good initial test, even if you don't let them run to completion
<gatecat>
(which is likely to be a multi day process)
<vup>
the problems unfortunately seem to mostly occur in the end
<vup>
(atleast the exception I linked above only happend after ~2 hours)
<cr1901>
There's a nontrivial chance that your errors were caused by changes I made to accomodate MachXO2, and I only fixed the fuzzers as needed
<cr1901>
I didn't really worry about touching fuzzers I already ran because gatecat and I accepted at the time that the full flow from empty dbs to filled dbs was already broken/needed to be fixed.
<vup>
Interesting, I don't think the MachXO2 changes were the cause of this issue
<cr1901>
Well, that's why I didn't put a concrete bound on the odds its my fault :)
<vup>
:)
<vup>
gatecat: is it normal that running a unchanged fuzzer actually produces changes to the database? Running 001-plc2_routing produces this diff: https://paste.niemo.de/raw/ohohefipim.diff
<gatecat>
yes, there's a fixup pass at the end that folds these back into the muxes
<vup>
makes sense, thank you :)
<cr1901>
The fuzzers treat "no change to bitstream" as a fixed connection. Sometimes those "no changed to bitstream" connections are default outputs for muxes
<cr1901>
So dbfixup handles that
<cr1901>
Tho without opening up EPIC right now, ".fixed_conn F0 F0_SLICE" seems like a genuine fixed connection?
<vup>
are there any more interdependencies between the fuzzers (when starting from the current db), or can I just run some random fuzzers and then db_fixup in the end?
<cr1901>
I don't remember running into problems doing that
<vup>
great
<gatecat>
the only other thing is that the "copy" fuzzers need to be run after fuzzers producing the data that they copy between tile types