whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<Myrl-saki> Okay cool, so DP16KD just sets data as 0 if CS doesn't match.
<Myrl-saki> So I just have to reduce_or, I guess.
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<Myrl-saki> How do I use generate with strings lol?
<Myrl-saki> idk how to make the csdecode go "0b000", "0b001", etc.
<Myrl-saki> sformatf, I guess?
<bjorkintosh> what hardware are you fine folks using?
<Myrl-saki> I'm getting aliasing from port select.
<Myrl-saki> Err
<Myrl-saki> Address selection
<Myrl-saki> Okay weird. So seems like BRAM starts at ADA3 for 8-bit?
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