whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<abradd> It seems that the source of the above issue is when only one signal is driving the tristate wire. If I add a second assign statement that drives the tristate wire everything works as expected.
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