whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<singham> I saw the asc files and there are 3 cells in hx8k, io_tile, logic_tile, ram_tile
<singham> What should I do to write asc file by hand?
<singham> Can someone help understanding internal logic of each of these tiles and their interconnects?
<singham> Is there an icestorm room?
<singham> Anyone?
<tnt> It would take _hours_ to explain this ...
<tnt> read the html files in icestorm.git/docs/
<singham> Does it have full gate diagram for the 3 blocks and interconnects? Sure
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