whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<singham> Hello
<singham> Yosys is a fantastic initiative. I would love to be active here
<singham> In nextpnr, if someone can help me find the chipdb step, I can help by lowering it's required RAM usage by contributing
<singham> I have failed in past to build it on RPI3, and I failed yesterday to build it
<singham> I use currently hx8k board
<jn> what do you mean by the chipdb step, and by finding it?
<singham> The step which requires lots of RAM to build
<singham> The code in python program which uses memory
<singham> block of code.
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<cr1901> If I have two modules that are similar (same I/O ports), Is there a way to run a select query that will return "cells in one module but not the other"?
<lofty> cr1901: select syntax is hierarchical, so if you know the name of that module you can use `c:foo/*`, IIRC
<cr1901> Hmmm, nope "select c:leds-bad/*" selects nothing
<cr1901> "select leds-bad leds-good %i" returns nothing as well
<cr1901> (although I guess that's not surprising, seeing that the intersection is technically... nothing. yosys can't figure out which cells are "the same" in between two modules)
<jix> cr1901: I don't think there is a way to do it with only a select query, but there might be other ways
<jix> also when do you consider a cell to be in both modules? will it have the same name? or do you want some structural comparison
<cr1901> structural comparison
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