whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<st3llar> wasted a few hours experimenting, but the answer was in the suggested (* no_rw_check *)
<st3llar> the extra circuitry is to ensure read-first or write-first behaviour
<st3llar> also found this document for memory patterns: https://docs.google.com/document/d/1MR1IV34XGJBIGMYu2YzjE-2KaNaP3R9jaPLj1RTU2j0/edit#heading=h.hxvjs26wvyc6
<tpb> Title: Memory Inference Patterns - Google Docs (at docs.google.com)
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<lofty> what was the point of fixing Yosys to correctly handle this if people will forever reach for the "I want to cause bugs" switch...
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<st3llar> just learning, and now I can appreciate yosys even more :)
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<lofty> st3llar: so, if you use that attribute you technically have a simulation/synthesis mismatch
<lofty> By the way, instead of relying on internal Google docs that I may or may not have leaked
<tpb> Title: 10. Memory mapping (at yosyshq.readthedocs.io)
<lofty> (and that documentation started out as a blog post I was going to make)
<st3llar> oups i somehow forgot about the manual, thanks a lot!
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