ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<jevinskie[m]> Are you using multiple verilator threads?
<qball1> no
<qball1> I made is completely single threaded
<qball1> to be sure
<qball1> *it
<qball1> I suspect I know what it is, I have normally have a memory mapped interface between the design and external world. In this case a dual port memory. I use the pub header in verilator to get the memory array, and read/write from there.
<qball1> reading goes fine, with writing I see an older value sometimes return.
<qball1> this happens when at the same time (from what I can deduce) the bram has a read at the same address.
<qball1> so I guess it is how the simulator works.
<qball1> not sure if I can work around this.
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