MoeIcenowy has quit [Read error: Connection reset by peer]
MoeIcenowy has joined #yosys
gordonDrogon has quit [Ping timeout: 240 seconds]
gordonDrogon has joined #yosys
GenTooMan has quit [Ping timeout: 244 seconds]
acathla has quit [Ping timeout: 240 seconds]
acathla has joined #yosys
GenTooMan has joined #yosys
GenTooMan has quit [Ping timeout: 240 seconds]
GenTooMan has joined #yosys
GenTooMan has quit [Ping timeout: 244 seconds]
MoeIcenowy has quit [Ping timeout: 240 seconds]
kraiskil has joined #yosys
kraiskil has quit [Read error: No route to host]
kraiskil_ has joined #yosys
MoeIcenowy has joined #yosys
kraiskil_ has quit [Ping timeout: 240 seconds]
kraiskil_ has joined #yosys
GenTooMan has joined #yosys
kraiskil_ has quit [Ping timeout: 240 seconds]
kraiskil_ has joined #yosys
GenTooMan has quit [Remote host closed the connection]
GenTooMan has joined #yosys
grmbl has left #yosys [#yosys]
kraiskil_ has quit [Ping timeout: 272 seconds]
<josuah>
ikskuh: hello! late answer, sorry... I had some troubles with verilog features not being supported by yosys
<josuah>
so eventually there will be warnings issued
<josuah>
if you suspect one signal in particular, you could also inspect the """ "bits": { 1, 2, 2, 3, 3, 3, 3 }, """ (example numbers) sections of the verilog file
<josuah>
if instead of numbers, there are """ "bits": [ "x", "x", "x" ] """, but the signal should be used, maybe something wrong did happen
<josuah>
in that case, upgrading yosys could eventually help
<ikskuh>
josuah: thanks, i figured it out
<ikskuh>
i was ... quite stupid :D
<ikskuh>
what also happened was that the bram took some clocks to be initialized
<ikskuh>
so the first memory fetch was still 0
<josuah>
I am not sure I could figure as much :) glad it did!
<ikskuh>
yeah, i'm pretty good at debugging random shit ^^
<ikskuh>
logic analyzer with 8 bit output is quite helpful
<ikskuh>
last thing i logged was just the data on the bus
<ikskuh>
and i recognized "B7" which was the second data word
<ikskuh>
and before that was "00" which was definitly not what i was expecting
<ikskuh>
introducing a 3 clock delay and it worked
<josuah>
in the various tooling for HDL, I see a lot of coverage for the happy path, but not so much for the "oops, that went unexpected"
<josuah>
like large complex verification libraries and ecosystem
<josuah>
but what if you need to debug a bug *through* all of these layers, with no idea on which layer it might be
<josuah>
for that, having a very thin layer and tools targetted at inspection help
<josuah>
> logic analyzer
<josuah>
like this :)
<josuah>
ikskuh: may I ask which one do you have?
<josuah>
I had not much luck with sigrok on my side