ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<josuah> hello! I am trying to get yosys talk SystemVerilog interfaces
<josuah> but it looks like the signals got stuck in traffic
<josuah> looking at my generated synthesis.json, I see plenty of list of signals (bit per bit) for plenty of things:
<josuah> such as: "gpio_rgb": { "direction": "output", "bits": [ 5, 6, 7 ] }, ...
<josuah> when I instanciate an interface on a module ("iSpi spi ();"), it is happy and fils all the "bits" everywhere on that module
<josuah> but when I pass that instanciated interface to a submodule, the bits become "x", "x", "x", "x"
<josuah> Verilator is not reporting anything going wrong, and the simulation runs fine
<josuah> so I wonder: is it known that SystemVerilog interfaces are not there yet in yosys? Then I could try to look what I could eventually do.
<josuah> or if they are reported to work, I can dig deeper onto my own verilog source.
<josuah> if this message falls in the abyss of the backlogs of everyone, I will report a proper issue on the repo anyway...
<josuah> thank you everyone!
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