<Sarayan>
ikskuh: If you can use explicit i/o primitives with output and enable pins so that there is no Z involved
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<mwk>
ikskuh: the assign should work, tristates are supported enough for that pattern
<mwk>
the warning is kinda overzealous
<mwk>
I hope the pin is not literally named `output` though, that'd be a keyword
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<jix>
ikskuh: that pattern (a mux with one side being all-z) gets turned into a $tribuf cell by the tribuf pass, that pass gets run qutie early by synth_ecp5 (see help synth_ecp5 for the sub-passes it runs)
<ikskuh>
okay, cool
<ikskuh>
thanks
<jix>
ikskuh: so if it doesn't behave as expected, manually running the first few passes up to and including the tribuf pass and then looking at the output (using show) might help
<jix>
when using show you probably want to use a small test design though, otherwise it will just hang trying to layout a way to complex graph of the RTL
<ikskuh>
i found a better solution tho: i just pass-through the SPI through my FPGA instead of sharing the bus externally
<jix>
that sounds like it also makes debugging on the electronics/actual HW side easier :)
<ikskuh>
yep, exactly
<ikskuh>
it also allows me to maybe use that channel for other tasks later