ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<ikskuh> heya o/
<ikskuh> Warning: Replacing memory \data with list of registers. See src/fifo.v:54, src/fifo.v:48
<ikskuh> is that a bad thing?
<xiretza[m]> depends on how big your memory is
<ikskuh> 64 bit in that case
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<xiretza[m]> might be fine then, it should tell you somewhere why it's not using block RAM
<xiretza[m]> might just be too small to bother
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<ikskuh> is block ram automagically deduced?
<xiretza[m]> well, yosys tries to do that, but it's not always very good at it
<ikskuh> ah, thanks :)
<ikskuh> both Verilog and yosys is very new to me
<ikskuh> i have some experience with Lattice Diamond and MachXO{1,2,3}
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<ikskuh> i should learn how to run a simulation/workbench ^^
<ikskuh> "my code doesn't work, it needs debugging"
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