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<bluesceada>
xiretza[m], yeah but we wanted to have an open-source toolchain, or is there vhdl support in yosys by now? I personally also learned VHDL before verilog, but I like verilog more by now. If it has enough errors/warnings it should also be fine, imho
<bluesceada>
lofty, thanks, I will have a look. But I guess that will not make the warning an error?
<tnt>
There is a ghdl plugin for yosys to add vhdl support.
<bluesceada>
tnt, the last time I tried that didn't really work well
<tnt>
Heh, no idea, never tried it ...
<bluesceada>
anyway, because that was the case, we changed all our experiments from vhdl to verilog ... that was 2-3 years ago or so
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<lofty>
bluesceada: yes, it makes it an error
<lofty>
-e regex
<lofty>
if a warning message matches the regex, it is printed as error
<lofty>
message instead and the tool terminates with a nonzero return code.
<bluesceada>
lofty, ah thanks, that's nice
<bluesceada>
but something like -Werror (makes all warings errors) is not available?
<tnt>
that'd be useless really because some warning can't be suppressed and are perfectly valid verilog.
<tnt>
(the "converting to multiple register" thing when using arrays comes to mind.)
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<bl0x>
@bluesceada last time I tried the ghdl plugin for yosys it was working fine. I used it with apio then.
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<xiretza[m]>
<bluesceada> "tnt, the last time I tried..." <- I can agree with bl0x there, it works pretty well nowadays
<gatecat>
ime if you do hit specific bugs they are fixed pretty quick too
<gatecat>
at least when I last played with it
<bluesceada>
ah ok, thanks, but yeah too late for now, our experiments evolved since they got converted to verilog
<bluesceada>
and probably it would be more effort than just installing oss-cad-suite ? which is better to support the students when it is just a single install...
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