ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<Guest65> I built yosys 0.12 . I still can't clear the xilinx tests
<Guest65> the ones within tests/arch/xilinx
<Guest65> It shows error Makefile:808 Error 2
<Guest65> If someone is on arch, one can uncomment check function on above link, execute makepkg and reproduce the error
<Guest65> Please help in case the error is not in the software itself.
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<Guest656> Does anyone know Andres Navarro?
<Guest656> Probably born in 82
<Guest656> module clock_generator
<Guest656>   (input clk,
<Guest656>    output clk_vga,
<Guest656>    output reset_vga
<Guest656>    );
<Guest656> I have this 3 parameter module which has been instantiated using 5 parameters. Is this valid?
<Guest656> clock_generator clock_generator(.clk(clk),
<Guest656>                                    .clk_usb(clk_usb),
<Guest656>                                    .reset_usb(reset_usb),
<Guest656>                                    .clk_vga(clk_vga),
<Guest656>                                    .reset_vga(reset_vga)
<Guest656>                                    );
<Guest656> Like this
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* cr1901 thinks the topic should mention that "IRC is async" and to "stick around for a few hours"
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