ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<Guest85> I met a problem when using Yosys to synthesis a verilog file. In a verilog module I declared a parameter, say parameter MIN = 4. Then, I synthesis it, and I got a correct results. However, when I overwrite the parameter outside the module with the same value (defparam mod.MIN = 4;), and redo the synthesis, the results is wrong. I believe this is
<Guest85> the only change. Don't know why this could happen
<Guest85> I need to change the parameter, can someone help to solve this myth?
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