<jenneron[m]>
digetx: sorry, i still don't understand something about clocks
<jenneron[m]>
i want to set uartc to 48000000 (default is 1875863) and pwm to 3187500 (default is 48000000). both are children of pllp and seem to divide correctly: 408000000 / 48000000 = 8.5, 408000000 / 3187500 = 128
<jenneron[m]>
i'm trying to do it with assigned-clocks binding, but it doesn't change anything in clk_tree. bindings: https://dpaste.com/DGCWTGHXV
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<digetx>
add "tp_printk trace_event=clk_set_rate,clk_set_parent" to kernel cmdline and find where it's changed in code
<jenneron[m]>
am i correct that solving this is basically adding a "clock-frequency" DT property and parsing this in drivers like clock-bindings.txt suggests?
<digetx>
I don't understand what you trying to achieve
<digetx>
that is pwm controller clock, not output pwm rate
<jenneron[m]>
bluetooth fails with failed to write clock error, uartc clock frequency is much lower than one from downstream clk tree (1875863 vs 48000000)
<digetx>
uart has internal divider
<jenneron[m]>
in addition: if i reboot from android (adb reboot bootloader) uartc frequency is 62769231 and bluetooth goes farther (tries to load firmware)
<digetx>
you won't see it in clock tree
<digetx>
for pwm you need to set rate using pwms phandle
<digetx>
bluetooth and wifi are the same chip, if it's not powered and reset properly on cold boot, then it all won't work
<digetx>
uart speed of bluetooth is limited by max-speed in device tree, see bluetooth node of N7 and other devices
<digetx>
serial driver will set the rate, so you don't need to touch it, you may change the parent clock
<digetx>
you also should use nvidia,tegra114-hsuart for bluetooth, not regular uart