07:14 <DavidHeidelberg> digetx is ehci from tegra30 compatible with tegra20?

12:52 <jenneron[m]> digetx: hi, am i correct that this value https://github.com/jenneron/linux-asus-tf701t/blob/tf701t-new/arch/arm/boot/dts/tegra114-asus-tf701t.dts#L745 should change 48000000 to 52000000 here https://dpaste.com/AR5ETYZ26#line-58? it doesn't work for me

14:12 <digetx> DavidHeidelberg: incompatible

14:14 <digetx> jenneron[m]: 52 won't work, the clock rate should be integer-divided from the parent rate and it's 408MHz for PLLP

14:19 <DavidHeidelberg> thx

14:19 <DavidHeidelberg> digetx and ehciXXX are backwards compat with 30?

14:22 <digetx> what ehciXXX

14:36 <digetx> if you mean later soc versions, then they are compatible with t30

14:40 <DavidHeidelberg> digetx y, thx

17:22 <jenneron[m]> digetx: then why 48000000 "works"? 408000000/48000000=8.5

17:32 <jenneron[m]> so considering "These include not only the standard handset reference frequencies of 19.2, 19.44, 19.68, 19.8, 20, 26, 37.4, and 52 MHz, but also other frequencies in this range, with approximately 80 Hz resolution.", so according to this 51000000 is the biggest it may work with 408000000 / 51000000 = 8, but it is unclear for me what means approximately at this point

17:39 <digetx> ah, sdmmc has 7.1 divider

17:45 <digetx> it's 7bit integer + 0.5

17:46 <digetx> or + 0

17:46 <digetx> so 8 and 8.5 are valid

18:14 <jenneron[m]> what does it mean

18:25 <jenneron[m]> so 51000000 is still the biggest one

18:32 <jenneron[m]> anyway i changed clock to 51000000 and it is still 48000000 in clk_summary

18:59 <digetx> mmc driver should set to 50MHz

19:12 <jenneron[m]> digetx: do you have ideas?

19:31 <digetx> about what

19:34 <digetx> 50MHz is maximum supported by the WiFi card and MMC core gets that info from the card

20:37 <jenneron[m]> but 408000000 / 50000000 = 8.16

20:39 <digetx> clock rate normally is rounded down

20:43 <jenneron[m]> mmc frequency should be same to clock, parent clock is pll p which is 408000000

20:44 <jenneron[m]> datasheet says 52

20:45 <jenneron[m]> ok, so i have... (full message at https://libera.ems.host/_matrix/media/r0/download/libera.chat/795f1e39eb0d3c86c7236af1231db93cd7efec26)

20:51 <digetx> you can't get 50 from 408

20:52 <digetx> you can get it from pllc3, but that will require to correct the mmc mux in clk driver for t114

20:53 <digetx> ah no

20:53 <digetx> the mux is okay in the code

20:53 <digetx> set parent to PLL_C3

20:55 <digetx> or C2

21:15 <kwizart> DavidHeidelberg, hi, I don't have schematics for paz00, what's is your issue with backlight ?

21:53 <jenneron[m]> ok, even if 50 is correct, i can't set it, it's still 48

21:59 <jenneron[m]> yes, but how then i should set mmc to 50 MHz?

22:00 <jenneron[m]> sorry for dumb questions

22:11 <jenneron[m]> brcmfmac still hangs, but it seems like i'm done with clocks

22:11 <jenneron[m]> thanks

22:25 <DavidHeidelberg> kwizart just filling mission DTS fields :) pwm backlight must have power-supply property :)

22:26 <digetx> jenneron[m]: if you will change parent to pllc, then you will get 50

22:26 <digetx> if it doesn't work, then you're using wrong dtb

22:28 <digetx> clock rate won't help hangs, it's usually related to other things

22:28 <digetx> check pinctrl driver strength

22:29 <digetx> try firmware from Android

22:29 <digetx> *drive

23:06 <jenneron[m]> my drive strengths for sdio are same to downstream

23:06 <jenneron[m]> clock thing works

23:07 <jenneron[m]> i'm 99% sure firmware is not the issue. wifi used to work for 2 days with this upstream firmware, but i lost this success after one cold boot

23:08 <digetx> check reset and power gpios

23:09 <digetx> you will lose wifi after another cold boot if they are incorrect/swapped