<azonenberg>
PCIe gen3 on 13 GHz active differential probe (top eye), through an AKL-PT5 with cable de-embedded (middle eye), and AKL-PT5 with cable and probe de-embedded (bottom eye)
<azonenberg>
Not super pretty but very much open enough to decode
<azonenberg>
Have to start actually writing the decode stack next
<azonenberg>
CDR on 1.08 Gbps data looks all good for a while then goes haywire and - this is the weird part - achieves a new stable lock at some multiple of the input
<azonenberg>
then about 2ms later, it makes another huge jump and, in the existing code on git, crashes or hangs because the period goes negative
<azonenberg>
i.e. the error term exceeds the NCO period
<azonenberg>
i added some error checks to abort the filter when this happens, just break out of the inner loop but keep all output generated up to that point
<azonenberg>
and... this is a tricky problem to debug lol
<Degi>
I mean the bottom eye with both deembedded looks smaller than the top eye with no deembedding
<Degi>
Huh
<Degi>
I find it interesting that the CDR frequency slowly increases, is it implemented as a filtered PLL or so?
<azonenberg>
It's a bang-bang control loop
<azonenberg>
but it scales the correction when running open loop due to lack of toggles in the input
<azonenberg>
So it applies a fixed correction to every edge in a 1-0-1-0 pattern, ignoring the magnitude of the error term and considering only the sign
<azonenberg>
but in a 1-1-0-0-1-1-0-0 pattern it applies twice the correction because the time of drift was twice as long
<azonenberg>
again ignoring the magnitude of the error term