<azonenberg>
Hardware update, for anyone following the logic analyzer work on my sata sniffer board: as of last night i can arm the trigger, capture compressed sample data for a pre-trigger window (currently hard coded 256 clocks)
<azonenberg>
wait for a trigger event (currently hard coded 1, i.e. instant trigger)
<azonenberg>
capture compressed sample data for a post trigger window (currently hard coded 256 clocks)
<azonenberg>
then flush all of the partial data stored in fifos and compressors out to DRAM
<azonenberg>
and set a "capture done" flag
<azonenberg>
The next step, not yet started, is building a readback path so that i can actually take this sample data and send it somewhere useful
<azonenberg>
in parallel with that, I'm working on a little MCU board i can hang off the FPGA to run a SCPI interface compatible with glscopeclient for command/control
<azonenberg>
that will be control plane only, the data plane link will terminate on the FPGA