<d1b2>
<esden> @azonenberg ok the bridge should be back up and running now ...
<azonenberg>
woo irc bridge is back
<azonenberg>
So I think at some point in the not too distant future I'm going to try designing a JESD204B testbed board
<azonenberg>
Not a super near term priority, but basically the idea is to find the cheapest adc i can find with a serdes interface, design a trivial frontend for it, and write some fpga glue to work with it
<azonenberg>
among other things i want to see how glscopeclient and libscopehal keep up with a faster data stream than the picoscope can spit out
<azonenberg>
The AD9683 seems like a good choice. 14 bit, 32-QFN, 14 bit, available in 170 Msps ($68.74 @ digikey qty 1) and 250 Msps ($117.13) speed grades
<azonenberg>
170 Msps is slow but the point isnt to build a usable scope, it'd be developing the back end for handling serial adc signals etc
<azonenberg>
Also oooooooh, the AD9083 looks fun. *16 bit* resolution, 125 MHz BW, 2 Gsps
<azonenberg>
but wait, it's 16 inputs? how does this work
<azonenberg>
oh, seems it has digital downconversion that you can't bypass :(
<azonenberg>
The AD9094 could be fun too. four independent 8 bit 1 Gsps converters for only $151. That's significantly cheaper than four HMCAD15xx's
<azonenberg>
So it looks like it has two pairs of converters, each sharing a 2-lane jesd204 link
<d1b2>
<Darius> "170 Msps is slow" lolz
<azonenberg>
Well i mean if you're talking JESD204B ADCs, it is
<d1b2>
<Darius> yeah I know
<azonenberg>
most slower stuff is parallel or spi or something
<d1b2>
<Darius> just hilarious when at work we sell VHF radars with muuuuuch lower sample rates
<azonenberg>
If I ever build a radar its going to be a C-band AESA working in the 5.8 GHz ISM band
<d1b2>
<Darius> we look for meteors
<d1b2>
<Darius> 5.8GHz is probably a bit high to get 70+km up
<azonenberg>
I'd be running at <1W total PEP across the whole array to stay within ISM power limits
<d1b2>
<Darius> yeah luckily someone else here with a physics PhD handled that stuff 😉
<d1b2>
<zyp> I grew up right next to that
<d1b2>
<Darius> !
<d1b2>
<Darius> small world
<azonenberg>
433 elements, 800 kW, 53.5 MHz? yea thats a pretty good sized array
<d1b2>
<Darius> I've been there a few times
<d1b2>
<Darius> yep
<d1b2>
<Darius> each antenna has independent transmit and receive phase control
<d1b2>
<Darius> it's nice in summer, not so much in winter though...
<azonenberg>
anyway so i'm thinking, the AD9094 would probably adapt quite nicely to the front end we had planned for BLONDEL et al
<azonenberg>
The only potential issue is that we would need to use a kintex-7 in ffg676 to back it
<azonenberg>
because keeping up with the data output would require running every one of the four jesd204 lanes at 10 Gbps
<azonenberg>
so if we used fbg484 we'd have no serdes lanes left over to run the 10GbE interface
<azonenberg>
My thought is that we could design a half-chassis width PCB that contained four frontends, one adc, a sodimm of ram, an fpga. and then a serial link to the other board
<azonenberg>
then have two of them, using an extra serdes lane to link them, in a full 8-channel system
<azonenberg>
to do 4-channel you'd just not fit one of the two boards
<azonenberg>
I guess if you wanted to be cheap there's always the option of only having 1000base-T but that strikes me as a bad idea
<azonenberg>
since one of the things that makes our hardware unique is that we have the high streaming performance
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<Degi>
Hm, for BLONDEL? Won't a HMCAD1520 be cheaper and better there?
<Degi>
(I think it'd better fit DUDDELL, or do we want 12 bit there?)
<Degi>
The AD9094 has some nice analog BW...
<azonenberg>
I'm not suggesting it to replace any existing design at this point
<azonenberg>
just musing about options
<Degi>
Maybe for a 8 bit version of ZENNECK, it'd save like 250 $
<azonenberg>
Well I'm thinking also pcb area and complexity
<azonenberg>
this is a single 32-qfn vs a zillion interleaved hmcad1520s
<Degi>
Hm yes
<azonenberg>
the problem like i said is serdes lanes, which is why i originally wanted to go with hmcad1520s
<Degi>
You ordered a few HMCADs, right? They seem to be uhh... out of stock
<someone--else>
it's also mostly compatible interface-wise with other fast AD ADCs with more bits
<Degi>
Hm yes, thats very nice
<azonenberg>
well yes, jesd204 is standardized
<azonenberg>
which is nice in terms of reusing code for other projects
<Degi>
Aren't the pinouts kinda standardized too?
<azonenberg>
That i dont know, but i'm more thinking code reuse
<azonenberg>
Anyway so going back to the pinout issues
<Degi>
I think I saw on some advertisement for JESD that at least some ADCs have compatible pinouts but different sample rate / bit number
<azonenberg>
kintex-7 fbg484 has 4x 10G SERDES, 185 HR IO, and 100 HP IO
<azonenberg>
ffg676 has 8x SERDES, 250 HR, 150 HP
<azonenberg>
The HMCAD1520 is fairly slow so we can use either HR or HP for the IO
<azonenberg>
Assuming we use DDR3 and a -2 speed FPGA with 2.0V VCCAUX_IO, you can do 1600 and possibly 1866 MT/s ram bandwidth (this seems iffy, there's a lot of footnotes) on HP, and 1066 in HR
<Degi>
AD9683 has a 1 GS/s variant at 14 bits and 2 GHz BW
<someone--else>
many AD GSPS ADCs are pin-compatible, but AD9094 might not be since it's 4 channels vs 2 for most others
<azonenberg>
Anyway, so assuming we use one GTX on the FPGA for 10GbE to the outside world, that leaves 3 or 7 depending on package available
<azonenberg>
Assuming we use a single 64-bit DDR3 SODIMM for buffer, we will need three banks (150 pins). Two nearly full for DQ byte groups and one with a few free signals for command/address
<azonenberg>
(But due to ground bounce the unused pins probably wont be usable for much else, and they'll have a weird SSTL Vref)
<azonenberg>
VCCIO*
<azonenberg>
There are not enough pins in FBG484 to do a full 64-bit ddr interface in HP banks so we would have to use HR there
<azonenberg>
So with FBG484 we get one lane of 10GbE, three free SERDES lanes, a 64-bit DDR3 1066 interface (66.625 Gbps peak bandwidth), and 135 available GPIOs after the RAM
<azonenberg>
With FFG676 we get one lane of 10GbE, seven free SERDES lanes, a 64-bit DDR3 1600 interface (100 Gbps peak bandwidth), and 250 available GPIOs
<azonenberg>
A single HMCAD1520 has ten LVDS pairs (20 pins) for data, plus some low speed SPI etc signals that we can drive from a MCU or something
<azonenberg>
and a clock that will come from a PLL not the FPGA
<azonenberg>
And the maximum throughput of data coming off each ADC is 8 bits * 1 GHz = 8 Gbps (12 bit mode is less than this)
<azonenberg>
So with FBG484, a single FPGA can physically fit six HMCAD1520s before you run out of pins. They'll put out 48 Gbps of data which will probably fit comfortably in the DDR3
<azonenberg>
That's plenty for a BLONDEL, and a bit over half of a DUDDELL. It will only fit one channel of a ZENNECK
<azonenberg>
In the case of FFG676, a single FPGA can physically fit twelve HMCAD1520s. They'll put out 96 Gbps of data which would barely fit in the DRAM, but probably be too tight after you consider overhead
<Degi>
Hm yes, ZENNECK probably needs the bigger package either way
<azonenberg>
I'm trying to limit to stuff we can do at a reasonable price
<azonenberg>
in particular i want to avoid ultrascale
<azonenberg>
as well as non-webpack parts
<azonenberg>
FFG676 is the largest kintex-7 package for the 7k160t which is the largest webpack 7 series hcip
<Degi>
How pricy are both package variants anyways? (webpack?)
<Degi>
Oh...
<azonenberg>
Moving to FFG900 requires going to the 325t
<azonenberg>
assuming -2 speed, current digikey pricing, fbg484 is $361.20, ffg676 is $520.80 (they've both increased significantly thanks to the shortages)
<Degi>
Hm, though the 484 and 676 seem to be pretty close in price (236 vs 273 € for -1, 284 vs 327 € for -2)
<azonenberg>
for comparison's sake the xc7k325t, the next die size up, in the same ffg676 package is $1953
<Degi>
They seem a bit cheaper on mouser but not available
<Degi>
oof
<azonenberg>
and if you go to ffg900, $2245
<azonenberg>
That's before the $3K or so for a full vivado license so you can actually develop for it
<Degi>
Maybe glue it together with a bunch of ECP5 in 756 package
<azonenberg>
Anyway, so basically the 325 is off limits
<azonenberg>
So now let's look at ultrascale
<Degi>
Oof, you pay for the chip and a dev license...
<azonenberg>
The xcku025 in FFVA1156 package will do at least 12.5 Gbps in all speed grade and package combos
<Degi>
The largest ECP5 is 54.75 € / 66.39 $ and has 365 IO... You could get like 10 of them instead of one ffg676 160t (though one 160t would be necessary for 10G interface)
<azonenberg>
And it's $994.50 at digikey and they actually have one in stock lol
<azonenberg>
It has 12x GTH transceivers and 104+208 HR+HP IO
<azonenberg>
gaah ok i'm just gonna make a spreadsheet of this
<Degi>
The IOs on the fast banks (I think 75 %?) can output a 900+ MHz signal (not sure how high the BER is), so at least the IO BW would be 260 Gb/s (assuming differential pairs)
<Degi>
12 transceivers sounds very nice for dual channel ZENNECK with the AD parts
<Degi>
Kinda wonder if you could attach one HMCAD1520 to one ECP5 with 4 SERDES and then one 4x 3.125 to 1x 10 Gb/s ethernet adapter IC to make a cheap sampling device (with no large internal memory, directly streaming to 10 GbE)
<azonenberg>
I mean it could probably be done, but i want buffer because things arent always going to be able to sustain 10G throughput
<Degi>
Well, it has like 18 Mbits of block RAM xD
<azonenberg>
Hmmmmmm
<azonenberg>
So kintex ultrascale supports DDR4 which gives a lot more RAM BW
<azonenberg>
and they also have a pretty good number of serdes
<Degi>
(Which is enough for 2.25 ms)
<Degi>
JESD204B would be very nice for the larger designs...
<azonenberg>
So with the cheapest kintex ultrascale we could have a DDR4 1866 SODIMM (or 2133 if we bump up a speed grade)
<azonenberg>
and host two AD9094s for a total of eight 1 Gsps 8-bit channels. Which is basically what we had planned for DUDDELL
<azonenberg>
plus a lane of 10GbE and three uncommitted serdes lanes
<azonenberg>
I think 1866 would be enough ram bw given the ADCs only put out 64 Gbps of data
<Degi>
Hm, could you use the four lanes for 40 GbE and 10 GbE and a MUX switch IC?
<azonenberg>
I could but I think 40G would be unnecessary for equipment at that performance class
<azonenberg>
and its a fair bit more work
<azonenberg>
The question of course is, is it worth building a scope with a $1K FPGA that is only 8 channels 1 Gsps 8 bit?
<Degi>
Hm, the whole MSO5074 cost 1 k€ and has 4 channels and 8 GS/s total
<azonenberg>
We are not going to compete with Rigol on price. It's just not going to happen
<azonenberg>
they have custom asics and large production volume
<Degi>
Well, if the rest is about 1-2 k$ it should be fine
<azonenberg>
we have neither
<azonenberg>
anyway, if we wanted to target more high end stuff the AD9690BCPZ-1000 might be worth looking at
<azonenberg>
let me see if we can bypass the downconverter
<azonenberg>
Yah it seems we can bypass decimation and downconversion and do real output at 1000 Msps
<Degi>
Hm yes, there is a direct arrow on top of it... 14 bit would be very nice
<GyrosGeier>
can you have multiple RAM interfaces and combine them?
<azonenberg>
I mean yes we can do multi channel and allocate some ram to different adcs or something
<azonenberg>
But that means way more pins
<Degi>
And the incredible BW and 400/200/100/50 ohm termination, we could parallel 8 of them with simple passive splitters
<azonenberg>
in the package sizes we're discussing right now, that's not plausible
<azonenberg>
On four JESD204B lanes for a single 14 bit ADC though
<Degi>
Hm yes, if we parallel 8 for 8 GS/s 2 GHz, then you have 32 lanes...
<Degi>
And 3200 € of ADC per channel O.o
<azonenberg>
So it looks like we might be able to run with two lanes at 16 bit padded sample size at 10*Fout
<azonenberg>
so 10 Gbps per lane, two lanes is 20 Gbps, 14 bit * 1 Gbps plus framing overhead will fit in that
<Degi>
Hm, is it 8b10b?
<azonenberg>
Yeah
<azonenberg>
They can actually run up to 12.5 Gbps per lane
<Degi>
Oh nice, you can skew and delay the clock
<Degi>
If you feed it a 4 GHz clock and divide by 4, it should be pretty easy to run 4 in parallel
<azonenberg>
Yeah, so that would be 4 Gsps 14 bit which is pretty nice. But again you run into issues of FPGA capacity
<azonenberg>
Do you have any idea how much FPGA you need to run eight jesd204 lanes? :P
<Degi>
(And fine delay for the rest, if you run it at 4 GHz you have 250 ps rough steps and then +- 150 ps adjustment)
<Degi>
As in fabric or the number of serdes lanes? xD
<azonenberg>
serdes lanes, as well as GPIO to run all of the RAM you need to buffer that data
<azonenberg>
the smallest fpga that can run four ad9690s while still having a lane free for 10GbE is the xcku025
<azonenberg>
so you're back in "one FPGA per channel" territory except now it's a $1K FPGA
<someone--else>
AD9213 is nice
<Degi>
Yeah and four of the ADC costs 1600 $
<azonenberg>
someone--else: AD9213 is already the adc i plan to use for our highest end scope
<azonenberg>
way down the road
<Degi>
Is the 14 bit ADC for ZENNECK?
<azonenberg>
I have no specific plans for target deployments of any of these chips yet
<azonenberg>
Just rethinking roadmaps
<Degi>
Oh, it only has 10.8 ENOB at 10 MHz and 9.8 ENOB at 1 GHz
<Degi>
The -500 variant has more ENOB
<azonenberg>
yeah but only 500 Msps
<Degi>
Maybe a 12 bit one would make more sense?
<Degi>
Though not sure how the ENOB is measured, with pk-pk or RMS noise? With the former it would still be quite good
<azonenberg>
Let's see, AD9625BBPZ-2.0. $959 @ digikey qty1
<azonenberg>
12 bit, 2.0 Gsps in this speed grade
<Degi>
Hm, thats more than double the price of the 14 bit one and has less ENOB
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<Degi>
What if for the higher end ones we have something like a PCIe slot with JESD204B lanes and a few pins for configuration and then you can swap out the AFE cards
<Degi>
At least for testing that'd be good since for a revision only part of the components need to be replaced
<azonenberg>
We can worry about physical architecture later
<azonenberg>
Anyway, just thinking, AD9625 is six lanes for 2 Gsps @ 12 bit. But those lanes actually run quite slow, up to 6.25 Gbps
<azonenberg>
Which is within the range of an artix-7
<Degi>
Ah and then we can use the cheaper FPGA and multiple of them?
<azonenberg>
We could hang two of those lanes off an xc7a200t in ffg1156
<azonenberg>
two of those chips*
<azonenberg>
let me add it to the table, sec
<azonenberg>
It does not have 10GbE
<azonenberg>
but we could use a 6G lane to talk to a kintex7 that would do that
<azonenberg>
It can do DDR3 800, or 1066 if you bump to the -3 speed grade
<azonenberg>
But given that we have 500 GPIOs, we could easily do dual channel per fpga
<azonenberg>
So, here's a proposal for something in the ZENNECK class
<azonenberg>
actually wait let me check one more thing
<azonenberg>
Ok, yeah so i think this is probably the better way to go as far as keeping things simple and modular
<azonenberg>
An XC7A100T-2FGG676C can go up to 6.25 Gbps per GTP transceiver
<azonenberg>
And has eight, plus 300 IOs
<azonenberg>
So we could design a channel card containing one FPGA, one SODIMM of DDR3 800, one AD9625, and one AFE
<someone--else>
these https://www.efinixinc.com/products-titanium.html might be nice once they are available. judging from existing Trion series, pricing would be much lower compared to X/A cartel
<someone--else>
sorry, it's amd/intel now
<someone--else>
again
<azonenberg>
Interesting
<azonenberg>
anyway, so this design would give us one 2 Gsps 12 bit channel per line card
<azonenberg>
We could also scale up to a 7a200t, dual channel ram, and two interleaved AD9625s to get 4 Gsps 12 bit per line card
<azonenberg>
Actually we could bump the ADC speed grade up to the 2.5 Gsps version and hit 5 Gsps 12 bit per channel
<azonenberg>
That's $1410 per ADC
<azonenberg>
With that, we could probably target 1 GHz bandwidth at least
<azonenberg>
BOM wise, we'd be looking at 2x $1410 ADCs + 1x $316 FPGA + PCB, frontend, and RAM
<azonenberg>
then a mainboard for them all to hang off
<azonenberg>
That would result in an instrument in the WaveSurfer 4000HD class
<azonenberg>
Their 1 GHz SKU sells for $17840
<Degi>
SKU?
<azonenberg>
model
<azonenberg>
And that's 4 channels. The 500 MHz version is $14780
<azonenberg>
We'd be looking at $3136 per channel plus frontend and support components
<azonenberg>
So certainly for a 1 GHz version, i think we could actually be price competitive
<someone--else>
wrt xilinx outrageous profit margins: xc7k160t die costs them $5; lowest digikey price at the moment: $279.5
<azonenberg>
$5? where did that number come from
<azonenberg>
it's a pretty decent sized hunk of 28nm silicon
<azonenberg>
and last time i checked 28nm wafer costs still weren't exactly CHEAP
<azonenberg>
i figured it was double digits at least
<Degi>
Actually what if we do a little bit of custom silicon?
<azonenberg>
for what?
<azonenberg>
there's no serdes ip on sky130 yet, although they're working on it
<Degi>
Idk, maybe for custom attenuators or so
<azonenberg>
a custom asic front end would not be outside the realm of possibility but sky130 isn't caught up to that yet
<azonenberg>
they're still getting their digital act together
<azonenberg>
its gonna be a few months at least before anything sane analog is plausible
<Degi>
I wonder how good direct beam writing is for this kinda stuff
<azonenberg>
We'll see where we are at that point
<azonenberg>
Aaaaanyway, back to the original discussion
<azonenberg>
Basically it seems like for higher end, jesd204 adcs and one fpga per channel is probably going to be the way to go
<azonenberg>
but for lower end, the hmcad1520 is probably still the best option
<azonenberg>
someone--else: then add packaging, test, etc
<someone--else>
also 50% digikey margins, yep
<azonenberg>
I expect they're still well into double digit range for what it costs them to manufacture
<someone--else>
still though
<azonenberg>
but yes, digikey has a huge markup
<azonenberg>
e.g. Win Source has the xc7k160t-2fbg484c for $133.20
<azonenberg>
With 238 in stock in the hong kong warehouse
<someone--else>
I think these chinese prices are more representative of actual prices high volume customers pay for the fpgas
<azonenberg>
Yeah
<azonenberg>
Anyway, so DUDDELL I think is plausible to build with a single kintex-7
<someone--else>
but I'm outraged still that they small companies have to pay full digikey price (notice there are even no volume discounts there unlike other parts)
<azonenberg>
yeah
<azonenberg>
With a 7k160t-2ffg676c we could fit eight HMCAD1520s comfortably, still have pins left over for other stuff
<azonenberg>
as well as a DDR3 1600 SODIMM giving 100 Gbps of RAM throughput, which even after overhead should comfortably fit the 64 Gbps of ADC sample data
<GyrosGeier>
Altera FPGAs seem to be more expensive at Win Source
<azonenberg>
and then a 10G lane and seven free GTXes (we could probably route out both a 10G SFP+ and a 40G QSFP+ on that)
<azonenberg>
GyrosGeier: those are made by intel, unsure where the fab is
<someone--else>
btw, HMCAD1511s are available from china for outrageously nice prices of $15
<azonenberg>
xilinx stuff is made at TSMC
<azonenberg>
so more readily available in china i'd imagine
<someone--else>
win source and similar distributors in china usually sell pcb production run leftovers, so what gets reflowed there is available; large alter and new xilinx chips (ultrascale and newer) aren't
<someone--else>
altera
<someone--else>
similarly, HMCAD1520 aren't
<GyrosGeier>
can you use all the GTXes on Xilinx FPGAs, or are there stupid restrictions like on the Altera ones?
<azonenberg>
what do you mean stupid restrictions?
<azonenberg>
the main restriction is that you have two PLLs per quad so you can use a max of two different data rates (and divisors thereof) per quad
<GyrosGeier>
e.g. they have one PLL per channel, and you have to decide whether to use it for TX or RX, and if you want it on the RX side, then you need to use either a neighboring channel PLL or one of the frequency limited fPLLs as your TX clock source
<azonenberg>
o_O
<azonenberg>
In the case of the 7 series GTX, the transceivers are grouped in sets of four
<azonenberg>
This contains a shared PLL, the QPLL, which you can share across all channels in the quad
<azonenberg>
as well as one channel PLL, the CPLL, per channel
<GyrosGeier>
so you'd use the CPLL for CDR
<azonenberg>
Each TX or RX can use CPLL or QPLL, with a separate divider, for each
<azonenberg>
No this is separate from the CDR
<GyrosGeier>
oooh
<GyrosGeier>
because Altera says that if you use CDR, the channel PLL is used for that
<azonenberg>
The CDR uses a phase interpolator clocked by either CPLL or QPLL
<azonenberg>
The CPLL can run up to 6.6 Gbps
<azonenberg>
The QPLL can run up to 12.5 Gbps depending on speed grade
<GyrosGeier>
heh, it's the other way round on the CycloneV
<azonenberg>
Anyway, the GTP transceiver is even more flexible IMO
<azonenberg>
there are two PLLs in the quad, fully independent
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<azonenberg>
The TX and RX can both independently divide off either
<GyrosGeier>
the channel PLL can go up to 6 Gbps, but the fPLL feeding the group (of three channels) can only do 3Gbps, so if you need 6 Gbps TX, you have to feed the group from the channel PLL of the middle channel
<GyrosGeier>
so one channel doesn't have a CDR PLL
<GyrosGeier>
it is kind of silly
<azonenberg>
yeah thats pretty derpy
<azonenberg>
i've never had problems with PLL exhaustion in any of my projects
<azonenberg>
if anything the limitation i ran into was that you have only two refclk inputs per quad
<azonenberg>
so you have to multiply off one or the other regardless
<GyrosGeier>
lol I have one refclk and I cannot distribute it anywhere else
<Degi>
Can't you take refclks from elsewhere for a pll in a different quad?
<GyrosGeier>
but that's a $100 FPGA
<azonenberg>
Degi: in xilinx's case there are two dedicated refclk input diffpairs per quad
<GyrosGeier>
the most annoying thing is that I can't send the GTX refclk to the rest of the fabric
<azonenberg>
hard wired and you can't use the ref from anywhere else
<azonenberg>
so for multi quad designs splitters/buffers are often needed
<GyrosGeier>
(or rather, I can, but only to a global clock network, which I can't use as a PLL input for one of the other PLLs)
<azonenberg>
Now, let's have another look at the AD9213...
<GyrosGeier>
how would you do PCIe x8? split the PCIe refclk?
<azonenberg>
Yeah
<azonenberg>
soooo... AD9625 in the 2.5 Gsps speed grade is $1410
<azonenberg>
The AD9213 in the 6 Gsps speed grade is $2192
<azonenberg>
So two AD9625s actually does not make sense anymore
<azonenberg>
Unless it becomes an issue for FPGA support...
<azonenberg>
let's see, the AD(213 has 16 lanes and can run up to 16 Gbps
<azonenberg>
AD9213*
<azonenberg>
If we clock it at 5 Gsps, we can run the JESD204 in 12 lane 6.25 Gsps mode if I'm reading this right
<azonenberg>
And have a single xc7a200t driving it
<azonenberg>
So no interleaving to worry about
<azonenberg>
So i guess the question is, is it still ZENNEC Kat this point? :p
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<azonenberg>
I think this design does make more sense for something in this performance class, vs having a zillion interleaved HMCAD1520s
<azonenberg>
and it will actually perform better (the original ZENNECK concept would need four HMCAD1520s per channel and only have got 2 Gsps in 12-bit mode)
<someone--else>
for the price of one AD9213 we can have 127 interleaved HMCAD1511 though..
<azonenberg>
someone--else: PCB space isn't free though
<azonenberg>
think about how many layers we'd need and how big the board would be
<someone--else>
that was a first-order estimate
<azonenberg>
also the timing and buffering and debugging needed
<azonenberg>
ZENNECK would have needed 32 HMCAD1520s
<azonenberg>
and interleaving that many might not even have worked
<Degi>
Don't you only need to interleave 4?
<azonenberg>
Yeah i mean for the whole system assuming 8 channels
<azonenberg>
But we'd also need lots of buffering. and performance would probably be bad wrt interleaving spurs and gain matching
<azonenberg>
because each HMCAD1520 is actually four ADCs internally
<azonenberg>
so we'd actually be doing 16-way interleaving per channel
<azonenberg>
a single adc is a much cleaner design
<azonenberg>
Soooo here's a new proposal
<azonenberg>
1) eliminate or indefinitely shelve BLONDEL
<azonenberg>
It'll be a lot of work and have bad performance because of sharing adc leaves among channels
<azonenberg>
and will be ~impossible to make price competitive with any mainstream offerings
<azonenberg>
2) DUDDELL stays basically as is. One XC7K160T-2FFG676 can handle all eight HMCAD1520s
<azonenberg>
without using any serdes lanes since they're LVDS not JESD204, so we have one for 10G and four for 40G if we choose to light up a QSFP too
<azonenberg>
and three unused
<azonenberg>
3) ZENNECK, rather than being an interleaved DUDDELL, becomes a scaled-down VOLLUM using the AD9213-6G instead of the AD9213-10G, and an Artix instead of a Kintex to run the JESD204
<azonenberg>
4) VOLLUM and MURDOCK basically stay as previously planned using the AD9213-10G
<azonenberg>
And DUDDELL would become the next scope project once we've debugged the active probe interface (which I haven't had time to touch...)
<GyrosGeier>
I should have written down the address of the dude I met in Tokyo
<azonenberg>
In other news, AKL-AD3 mechanical prototypes are at the post office expected to be delivered today
<GyrosGeier>
basically, large commercial building, had a ham radio shop over three floors in it, with a hole in the floors so they could show off a 10m antenna
<GyrosGeier>
and somewhere off the main path there was a small shop with a retired engineer selling self-built scopes
<Degi>
Hm, BLONDEL gets cancelled? Wasn't the AFE almost done? But yeah the price tag might be a big turnoff
<azonenberg>
Degi: BLONDEL, DUDDELL, and ZENNECK were originally planned to use the same frontend
<azonenberg>
just different antialiasing filters
<azonenberg>
I need one more spin to validate it after fixing some of the bugs i found the first time
<azonenberg>
But yeah it's ~done
<azonenberg>
We wouldn't be throwing away anything, really
<azonenberg>
We haven't done any work on the actual BLONDEL PCBs and that's the only thing we're axing
<azonenberg>
all of that tech would have been reused in DUDDELL and ZENNECK anyway
<azonenberg>
From my perspective BLONDEL is a cut-down DUDDELL that loses sample rate if you turn on more than two channels because there's only one ADC per quad
<azonenberg>
DUDDELL is the base model
<azonenberg>
then the originally planned ZENNECK was an interleaved DUDDEL
<Degi>
Hm, it still uses the HMCAD?
<azonenberg>
Yes. Original plan was BLONDEL = 4x AFE -> 1x HMCAD1520
<Degi>
Hm yes right that makes sense
<azonenberg>
DUDDELL = 1:1
<azonenberg>
ZENNECK = 1x AFE -> 4x HMCAD1520
<azonenberg>
I'm now proposing to use the lower end AD9213 for ZENNECK instead, and possibly boost the front end to have higher performance depending on whether we target 500 MHz or 1 GHz bandwidth
<azonenberg>
in either case I think 5 Gsps 12 bit for ZENNECK is a fairly firm target
<azonenberg>
Possibly six channels rather than eight
<Degi>
Hm, will there be a 4 channel version of duddell?
<azonenberg>
the rationale being that the kintex needs one serdes to each channel card and only has eight serdes lanes, so if we use one for 10G there's not enough. I'm also concerned about chassis space because i had been hoping to fit ZENNECK into 1U
<azonenberg>
but that will be figured out more once we have a closer to final design
<azonenberg>
At this time I'm thinking DUDDELL will be one motherboard with the FPGA, RAM, digital PSU, SFP+, and 1G PHY
<Degi>
How thick are the PCBs + parts? Maybe you could stack them (with cutouts for large parts on layers below)?
<azonenberg>
and eight channel cards each containing an AFE and an ADC
<azonenberg>
so you can scale arbitrarily
<azonenberg>
Interconnect between digital board and analog boards is TBD
<Degi>
Hm, the SERDES are bidirectional, right? Maybe unconnected TX lanes can be put on the connectors of the channel cards, in case you want a DDS channel or so
<azonenberg>
The HMCAD1520 uses LVDS not SERDES
<Degi>
Ah right, since its GPIO its bidi anyways
<azonenberg>
It's not implausible we could make a DDS signal generator that fits the same pinout
<azonenberg>
But also, the FPGA will have extra SERDES lanes
<azonenberg>
assuming we go with the ffg676 to get enough GPIO for the HMCADs, there will be eight lanes
<azonenberg>
if we use one quad for 40G (not in initial firmware, but pinned out in case we decide to use it) and the other quad has one lane for 10G
<azonenberg>
we will have three unused lanes
<azonenberg>
My proposal is to use two of those lanes as JESD204 for talking to a TBD DAC
someone--else has quit [Quit: Connection closed]
<azonenberg>
and provide a function generator
<Degi>
Hm yes
<Degi>
Actually a digital input card would be very easy to do if they have 10 LVDS lanes per channel
<azonenberg>
The plan had always been for there to be SFF-8087 connectors on the board for talking to a MEAD/CONWAY pod
<azonenberg>
exact number TBD depending on how many pins we have free
<Degi>
Ah yes with the leftovers, very good
<azonenberg>
This will probably be separate from the analog boards
<azonenberg>
Anyway, so i think we have a pretty firm plan now?