sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<aurel32> conchuod: i have been pointed that "clk: starfive: jh7110-sys: Add notifier for PLL0 clock" just got merged for v6.11-rc6
<aurel32> is there any plan to also get the DTS change for 6.11?
<conchuod> aurel32: At this point does it become required to avoid a regression?
<aurel32> i don't know, tbh i haven't tried to see what happens with only the first patch
<conchuod> The wording makes it seem as if it's avoiding an issue in patch 1, but maybe it is actually an issue in the fixes tag (but then why would they be in a series).
<conchuod> If it is fixing a regression that's caused by "clk: starfive: jh7110-sys: Add notifier for PLL0 clock", then I'll try to get it to Arnd this week. Otherwise, it can wait for 6.12 I think.
<conchuod> I can look into it myself, but likely not prior to Tuesday cos I've been on holiday and need to catch up on Monday.
<aurel32> ok thanks, i'll try a that tomorrow
<aurel32> or at least i'll try
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