sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<ball> I found myself thinking today about a quad-core RISC-V board but I should probably start out with something more modest.
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<unlord> ball: I have been recommending the Banana Pi BPI-F3 for hobbiests
<unlord> it has RVV 1.0 which is useful for doing optimization work
<palmer> ya, as long as you're OK with vendor kernels for a bit longer that's the way to go
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<ball> unlord: I think I've seen that somewhere. Let me look it up.
<unlord> I can give you a link if you can't find it
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<unlord> also, we are producing bootable SD images you can just download and use
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<chripo> //1
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<drewfustini> [PATCH 3/3] riscv: Allow to enable PREEMPT_RT
<drewfustini> "It is really time"
<bjdooks> I thought CONFIG_PREEMPT_RT was bsaically enabled for everyone, or has something changed?
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<palmer> bjdooks: I have also thought that many times, but there's always _something_ going on that we've forgotten about
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