sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<palmer> I got a cold, I'm going to have to skip the patchwork meeting tomorrow.
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<drewfustini> palmer: hope you feel better soon!
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<solol> That was random, drewfustini.
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<drewfustini> Palmer wrote last night that he has cold and won't make the patchwork call
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<Stat_headcrabed> seems jh8100 doesn't have vector support either
<Stat_headcrabed> sad
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<courmisch> wut?
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<Stat_headcrabed> ?
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<solol> WOOOOOOOOOOOAAAAAAAAAAAAAAAAAAAAATTT?
<Stat_headcrabed> ??
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<davidlt> it does has, the efficient cores incl. it.
<davidlt> Well, hopefully the didn't disable it.
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<drewfustini> wmat: thanks!
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<drewfustini> I was sad to miss that one, I'm glad there's video
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<courmisch> smaeul: uboot as a payload of SBI loaded by uboot just jams. No UDF. Just nothing.
<courmisch> at least with u-boot.bin as the payload
<smaeul> did you change the config option to build for S-mode?
<courmisch> smaeul: same same
<courmisch> well, I would have been surprised if vendor uboot magically worked in Smode by just flipping a switch
<smaeul> yeah unfortunately it will need some debugging
<courmisch> I don't like the look of that _start function
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<courmisch> anyone knows what the T-Head MCOR CSR does?
<smaeul> "cache operation register" for flushing I$/D$. definitely not accessible from S-mode
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<courmisch> that didn't help
<courmisch> well, not much to go on
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<courmisch> sigh, and it doesn't look like non-SPL u-boot can be convinced to support FW_DYNAMIC
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<drewfustini> from RISC-V Summit: Insight of Linux Distro Optimization for RISC-V: Using VisionFive 2 Debian as Example https://www.youtube.com/watch?v=eVGtSfEW8C0&list=PL85jopFZCnbMfMRR25ENcRkhhAUGwP5C5&index=74
<courmisch> sorear: not really. this is way beyond me.
<rbmarliere> ty for the links wmat
<rbmarliere> guys is the lichee pi the most performant soc currently available?
<gurki> id expect it to be beaten by the nvidia embedded stuff
<gurki> i checked since you made me curious. its beaten badly by stuff thats actually trying to be fast^^
<rbmarliere> pardon my ignorance, but which nvidia stuff?
<sorear> i'd say sg2042 but it depends on what you mean by "performant" and "available"... ET-SoC-1 allegedly exists
<gurki> the jetson family
<gurki> theres also the google tpu boards if you want to explicitely compete on the nn floor
<gurki> (none of these are riscv, but you asked in a generic way...)
<gurki> sorear: that sg2042 will be a brick soon if people stick to the plan of abandoning rvv 0.7 though
<rbmarliere> ah yeah I wanted to say riscv :)
<gurki> https://ui.adsabs.harvard.edu/abs/2023arXiv230900381B/abstract nice, you made me notice that people did proper benchmarking
<gurki> thanks! :)
<rbmarliere> i expect its not even a competition yet
<sorear> even if you ignore rvv entirely sg2042 still has the most total instructions/s of any hardware you can buy right now
<rbmarliere> sorear: available for purchasing
<sorear> if you're gonna call sg2042 a brick because it doesn't have rvv 1.0 you should call jh7100, fu740, etc bricks for the same reason
<rbmarliere> rvv is the new vector extension right?
<gurki> according to their findings it cant quite compete with intel broadwell :-|
<gurki> (unless im misreading, i need to spend more time on that paper before citing findings :) )
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<sorear> rvv is the standard risc-v vector extension (the only one, so neither new nor old)
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<gurki> rbmarliere: theres the one everyone implemented (0.7) and the one the rv crowd finally agreed on (1.0)
<gurki> which causes certain friction.
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<rbmarliere> thanks for the clarification
<sorear> if by "everyone" you mean "hardware shipped in 2023H1"
<jrtc27> "by people who willingly ignored the draft status of the spec"
<rbmarliere> hehe
<gurki> jrtc27: i tried to make my statement as neutral as possible to give him a proper response :)
<jrtc27> I made no statement there as to the wisdom or lack thereof
<sorear> i don't see any evidence, right now, that rvv 0.7 has displaced or precluded rvv 1.0; the cores that implement the draft spec would otherwise not have vectors at all or have an entirely vendor-defined mechanism. i'll be paying close attention to whether people ship 0.7 or 1.0 in 2024-2025
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<gurki> sorear: im just a little worried that these hw vendors get scared off after investing to produce stuff like the sg2042 that is outdated by the moment it hits the market
<sorear> if it makes you feel better the sg2042 doesn't have anywhere near enough memory bandwidth for the vectors to be properly useful
<sorear> so you can just pretend it never had vectors
<gurki> :D
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<courmisch> there aren't a whole lot of rvv optimisations available as of yet either way
<jrtc27> memory bandwidth for SIMD/SIMT is definitely not a thing in the introduction to computer architecture course here I teach my second year undergrads about...
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<sorear> not sure what you're trying to say there, I'm speculating that the sg2042 will run most data-intensive loops at 1 byte/cycle/core whether they use scalar or vector instructions because it's trying to share 4 memory channels 64 ways...
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