sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<courmisch> is Intel APX but an attempt to catch up to Aarch64 and RISC-V? 32 GPRs... nondestructivr instructione
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<suqdiq> courmisch lol TIL about that APX
<suqdiq> they used a similar name before
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<Stat_headcrabed> Esmil: Maybe this patch could fix kernel panic problems on JH7110’s crypto accelerator
<Stat_headcrabed> At least starfive stuff told me this..
<Stat_headcrabed> stuff(x) staff
<davidlt> this is still not fixed?
<Esmil> Stat_headcrabed: thanks! I'll try that out later
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<mml> i'm trying to make sense of C.SRLI[64] in RVC... https://paste.debian.net/1298344/ is the relevant extract from the spec
<sorear> SRLI64 means "shift by a count of 64", it's only meaningful for rv128
<mml> my target is RV64. the way i read that, 100100 mean shift right and 100000 is a HINT (may as well be a NOP)
<sorear> x >> 64
<sorear> are you a core/emulator designer or a compiler writer?
<sorear> as the former, you are required to treat HINTs as NOPs
<mml> i'm attempting to write a disassembler, so emulator designer is as close as i can get
<sorear> "nzuimm" applies to the entire field, not just bit 5; 100 0 00 001 00001 01 is «c.srli a1, 1» not a HINT
<mml> but what i'm trying to understand is why objdump says 0x8109 (which start 0b100000) is SRL when the spec makes it look like a HINT. the code does work, it's being emitted by GNU as and i did indeed write srli a0,a0,2 in the source code
<sorear> er, s1
<sorear> it's only a HINT if all six bits of the nzuimm shift count are zero
<mml> ok, i can go with that, but what does the text "nzuimm[5]=1" mean?
<mml> [5] means "the five bit integer"?
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<sorear> it's verilog syntax for bit 5 of a variable named nzuimm, i.e. the bit with value 32
<sorear> nzuimm[4:0] likewise means bits 4 through 0, inclusive and in that order
<mml> right, i get that... i think what confuses me is the string "nzuimm[5]=1", which seems like a qualifier... "this row applies when nzuimm[5]=1"
<mml> perhaps i don't grok what "RV32 NSE" preceding that means
<sorear> the immediate descriptions in chapter 2 use the same notation
<sorear> if nzuimm[5] = 1 (i.e., if the shift count is larger than 31) and in the RV32 case (in which case the only meaningful shift counts are 0-31), the opcode is designated for non-standard extensions (NSE)
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<mml> voila! thanks very much, now those tables make a lot more sense
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<courmisch> were there hwprobe flags for Zfh and Zvfh ?
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<smaeul> not merged yet
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<courmisch> I see thx
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