sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<bjdooks> hola amigos
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<bjdooks> hmm, whatever andes are doing to build uboot is causing (gcc?) to fail to build stack frames
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<bjdooks> anyone understand how the -msave-restore works on riscv, and if so can stack frame support be added
<bjdooks> or in fact if it is something uboot is actually using? i can't see to see anywhere it would get enabled
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<arnd> prabhakar: sorry for not having gotten back to the dma-mapping series yet. I still want to finish this, but you may need to decouple the riscv bits first. Since I took out the function pointers from the series, I don't think there is a direct dependency any more.
<arnd> you could take the riscv specific patches from my series as the base for your work though
<arnd> just to ensure that the semantics you use match up with what I had in my series for the common version
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<prabhakar> arnd: no worries. I already have posted the patches based on your series (https://patchwork.kernel.org/project/linux-renesas-soc/cover/20230412110900.69738-1-prabhakar.mahadev-lad.rj@bp.renesas.com/). Im just waiting for your bits to get in through and resend my series. I need to convince Christoph for this (as rest of the other risc-v maintainers
<prabhakar> are OK with non-coherent platforms).
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<palmer> arnd, prabhakar: FWIW, I'm fine with taking this sort of stuff into Linux -- sure it's ugly, but it's real HW so whatever
<arnd> which approach was the last version? My feeling is that the least ugly variant is the one where we have function pointers for specific nonstandard CPU cores, with an fallback to the standard zicbom version and a __likely/__unlikely annotation to make that the predicted branch.
<palmer> IIUC that's what Prabhakar's latest version was
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<arnd> ok, good. I think that should address any concerns about performance of the normal path, while also containing the complexity as much as possible, certainly less complex than using nested asm alternatives
<palmer> OK, LMK if you want me to do anything -- Christoph is very much not in agreement
<conchuod> It's your arch palmer ;)
<palmer> ya, but Christoph is smart so I'd like to at least understand what's up
<conchuod> Last time it sounded like he abhorred the non-standard hardware
<palmer> ya, I think everyone does
<palmer> I think he's not in IRC? maybe we should just talk more on LMKL?
<arnd> but the series he replied to still had the ALTERNATIVE_3 asm patching, which I think is just making it worse
<palmer> ya, looks like it's all inline still. I must have been thinking of a different think
<palmer> so I think if we add some sort of ALTERNATIVE_INLINE_OR_CALL, and then just hook up the non-standard flushing logic in C (for both Andes and T-Head) that'll be cleaner
<palmer> not sure that changes the core "we don't want vendor stuff in Linux" argument, though?
<conchuod> Correct me if I am wrong, but we went back the alternatives stuff arnd because Hellwig asked for it
<arnd> conchuod: I think that is correct, yes
<arnd> but if he's going to nak it either way, I don't see how that helps
<palmer> IIRC that was all function pointers, though? so with the patching we'd have the standard stuff inline and then a call for the non-standard stuff
<conchuod> I liked the "do function pointers if on a borked system, do zicbom otherwise" that was suggested here: https://lore.kernel.org/all/1c441d20-951d-407b-90ba-4cda3b0505b2@app.fastmail.com/
<palmer> IIRC the Andes stuff is just an SBI call, so at that point who cares about a function call
<conchuod> Who cares about a function call on any of the broken systems
<conchuod> At least they'll be working :)
<arnd> right, so something like this, to make it super explicit: https://www.irccloud.com/pastebin/JbgUW4BX/
<conchuod> Yeah, that LGTM.
<palmer> cool. Do you want to post on LKML? I'll try and remember to say I like it too...
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<conchuod> palmer: that was for arnd I assume?
<palmer> probably ;)
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<Stat_headcrabed> conchuod: I think Keith is not that familar with mainline submitting rules, so pointing out the problem directly would be better 🫠
<Stat_headcrabed> (Reply for that email
<conchuod> Stat_headcrabed: There's no rush in people learning :)
<Stat_headcrabed> 👍
<conchuod> Stat_headcrabed: Plus, some of the other StarFive folk should help him, since quite a few have upstreamed bindings now.
<Stat_headcrabed> Btw seems their emmc driver lacks something or sth, causing a performance regression.
<conchuod> I thought their mmc driver didn't even work with mainline yet, or am I forgetting something?
<Stat_headcrabed> I'm using their patch intergration tree for testing
<Stat_headcrabed> Noticed only about 2MB/s emmc speed on newer tree
<Stat_headcrabed> Which could reach 70+MB/s before
<conchuod> Oof
<Tenkawa> ouch
<muurkha> ow
<conchuod> I'll remember to keep an eye out for that then if nothing changes.
<Stat_headcrabed> I'm using hdparm --direct -t for testing
<Tenkawa> so it wasn't just my test cases that looked wrong...
<Tenkawa> I thought the numbers looked really low
<Stat_headcrabed> directly using dd still could get 70+M/s speed, but that uses RAM as buffer if I'm right
<Stat_headcrabed> Tenkawa: How you tested that?
<Tenkawa> oflag=direct
<Stat_headcrabed> I guess that's due to lack of clock configuration or something, but I'm not sure
<Tenkawa> nvme and usb looks fine... mmc looks terrible
<Tenkawa> (nvme still could be much better but its at least decent)
<Stat_headcrabed> SD card and emmc could reach 20MB/s without axp15060 series
<Stat_headcrabed> but it is worse now....
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<Stat_headcrabed> Btw, if anyone want to test this problem, I've got a working branch basing on an older version of their upstream intergration tree here: https://github.com/Headcrabed/linux/tree/axp15060_test_v3
<Stat_headcrabed> Remember to enable PMIC driver while testing
<Tenkawa> 1073741824 bytes (1.1 GB, 1.0 GiB) copied, 54.3089 s, 19.8 MB/s
<Tenkawa> I got that on a VF2 to microsd test
<Stat_headcrabed> That's a normal SD speed on vf2
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<Stat_headcrabed> Due to PMIC lacking enough power rails, SD shares vqmmc with other on-board peripherals at 3.3V, and that is the highest speed for SD spec on 3.3V
<mps> Tenkawa: what kernel you use on visionfive v2
<Tenkawa> 6.3.6
<Stat_headcrabed> But for emmc, there's a dedicated power rail for its vqmmc, and makes it possible to using 1.8V for higher speed(Needs correct regulator config in dts)
<mps> from which url?
<Tenkawa> mps: I'd have to go dig u p the bookmark.. its aurel32's
<Tenkawa> + patches
<Tenkawa> checking
<Tenkawa> yeah... I updated it to .6
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<Tenkawa> Linux vf2 6.3.6-vf2+ #5 SMP Mon Jun 5 08:50:13 EDT 2023 riscv64 GNU/Linux
<Tenkawa> I wish my Star64 could run 6.x... its still on 5.10 atm
<mps> Tenkawa: I've got V2 today and testing it little
<Tenkawa> Its fun...
<Tenkawa> (for me at least)
<Stat_headcrabed> SD/EMMC power design problem seems completely the same on Star64
<Tenkawa> Stat_headcrabed: I have been told it is
<Stat_headcrabed> lol
<Tenkawa> It is almost an identical JH7110 - the wifi and birfurcation of the USB
<Tenkawa> to allow for the pci-e
<Tenkawa> the pci-e may not be lightning... but its nice to have a full length slot
<Stat_headcrabed> I've seen someone already tried multiple PCIE gpus on that
<Tenkawa> really??? yikes
<Stat_headcrabed> PLDA's pcie controller is much better than Designware IP 😊
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<Tenkawa> Stat_headcrabed: oh I believe most potentially can/are better than DW
<Tenkawa> haahaa.. thats a setup...
<Stat_headcrabed> Wild but working
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