sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<muurkha> perhaps relevant to the question jrtc27 raised the other night of whether you should expect lower power usage from going from ARM to RISC-V: https://iis-people.ee.ethz.ch/~gmichi/asocd/lecturenotes/Lecture6.pdf
<muurkha> lecture slides from 7 years ago
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<muurkha> says the RISC-V Zscale got 138 DMIPS/MHz/mm2 and 1.8 microwatts per MHz in one 40-nm process and
<muurkha> the Cortex-M0 got 124 DMIPS/MHz/mm2 and 5.1 microwatts per MHz in another 40-nm process
<muurkha> so it's at least plausible that the RISC-V ISA has a real power advantage at the extreme low end
<muurkha> they also found an almost as big advantage for Rocket over Cortex-A5
<muurkha> maybe ARM has fixed some of their problems in the ensuing seven or eight years
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<drewfustini> Anyone other than Ben and Emil in Barcelona? I have created a signal group
<conchuod> @drewfustini Cyril should be there
<gurki> muurkha: thats a bit of an awkward comparison tho, they are comparing their optimized core vs a pretty random stm32
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<conchuod> jrtc27: the fear of no-map bothers me
<jrtc27> "X is inefficient, so lets use Y which doesn't work but hack around it and violate specs in the process to make it mostly work"
<jrtc27> *let's
<conchuod> 🙃
<jrtc27> perhaps a little facetious, but about how it appears on the outside not having followed things too closely
<conchuod> It's how it seems to me too chief
<jrtc27> (:
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