sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<bjdooks> phew, got back ok
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<conchuod> Took 2 days to get home from Dublin?
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* cousteau is not sure if that was for me
<bjdooks> conchuod: nope, two days to get back on irc
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<cousteau> tbf the Dublin airport was quite crowded...
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<leah2> anyone know of efforts for a buildroot-based toolchain for bl808?
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<leah2> anyone have a sipheed m1s dock? i'm having trouble getting into bootloader mode...
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<leah2> nvm my usb-c cable was defect -.-
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<palmer> leah2: I think the bl808 should run on upstream toolchains fine. There's some T-Head custom stuff that just got posted, but it should all be performance enhancements (ie, nothing necessary to run). There's also been some Linux code posted
<leah2> yes, i've setup a buildroot with vendor toolchain and kernel so far and will try to replace stuff
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<palmer> cool. The patches just got posted and are being reviewed, so if anything blows up it's a good time to say something ;)
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<conchuod> cousteau: hope you enjoyed your time here :) Was talking to mr dooks though as we were on the same flight from SFO -> Dublin
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<solrize> https://gustedt.wordpress.com/2022/12/18/checked-integer-arithmetic-in-the-prospect-of-c23/ hmm i'd rather have a software trap than a bool flag
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<solrize> but anyway this reinforces the idea that the lack of overflow checks in riscv was a mistake
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<jrtc27> says who
<jrtc27> for unsigned long overflow you just check if the result is less than one of the inputs
<jrtc27> single instruction, can be folded into a branch
<jrtc27> for signed long overflow it's (result <_s input) XOR (input <_s 0), and the XOR can be compressed
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<jrtc27> if that turns out to be an important operation going forwards then I guess a new extension can add a dedicated instruction for it
<jrtc27> fits an R format
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<Pokey> Hello!
<Pokey> Besides the technical documentation, are there any recommendations for learning in general about RISC-V? I did not take computer science, but I have a somewhat basic understanding of simple microprocessors (for example a Z80) and I wish to apply the small amount I do know to RISC-V, enough to understand how everything fits together, from bootloader, what OpenSBI actually means and where it fits in the system's hierachy to bootstrapping the Linux Kernel to
<Pokey> get us to a basic system. I'm very much a noob but a dream goal would be to take a RISC-V platfrom and set it up and run Linux with Busybox on it from scratch, and understand how each omponent of doing that fits together
<muurkha> sounds attainable
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<Pokey> muurkha: Certainly, just need to get my foot in the door somehow
<leah2> palmer: disabling CONFIG_VECTOR results in a booting kernel on gcc 11.3
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<muurkha> Pokey: wish I knew where to advise you to look
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<Pokey> muurkha: It's okay! Thanks anyway
<solrize> jrtc27, they went on a lot about not having overflow or carry detection because how that would mess up pipelines or something. even though they do it for floating point
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<jrtc27> yeah because fp is far more complex and you can't really infer the flags from the outputs and inputs without basically redoing the operation
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<solrize> checking for overflow with signed ints is slower than doing the operation in the first place too... whatever the obstacles were to checking in the hardware, they clearly weren't insurmountable
<jrtc27> well FP is often multi-cycle and has fewer functional units
<conchuod> leah2: heh, to be honest I wouldn't trust that vector implementation as far as I could throw it
<leah2> i'd be more happy to have wifi than vector, but that seems to be totally undocumented x_x
<conchuod> Does it not even work in their sdk?
<leah2> not with linux apparently
<leah2> and the sdk contains some blob
<conchuod> Perhaps it works with freeRTOS given the product page claims the Linux support is "basic" while freeRTOS is "full"
<leah2> i'll just wait for some ox64 folks to figure that out :p
<conchuod> Yah, the SDK doesn't look all that great ha