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kaaliakahn>
@Reinhilde! What are the choices? I have a RISCVI32 processor
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jrtc27>
ISA means nothing
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jrtc27>
what matters is what the interface on your cache is and what the interface on your memory is
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jrtc27>
AMBA, AXI, TileLink, Avalon, Wishbone, ...
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jrtc27>
many mostly-equivalent options to choose from for an interconnect
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jrtc27>
and whether you have DDR to talk to, SRAM, BRAM, etc will dictate what you put at one end
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jrtc27>
or if you want a TCM you can directly connect your cache to your memory
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jrtc27>
there is no answer to the question, just more questions
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kaaliakahn>
@jrtc27, there is DDR to talk to
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jrtc27>
are you writing the memory controller (probably not) or reusing some third-party/vendor IP?
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kaaliakahn>
reusing 3rd party vendor
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jrtc27>
so then the interface you need is whatever that uses
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kaaliakahn>
@jrtc27 any pointers to open source memory controller for RISCV that interface with DDR
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jrtc27>
idk, I'm not a hardware engineer, I'd just be googling like you
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jrtc27>
maybe opentitan has something, maybe zip has something
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jrtc27>
DDR generation is also going to be rather important though
<
jrtc27>
DDR2 and DDR5 are quite different
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kaaliakahn>
@jrtc27 Thanks so much
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