sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<kaaliakahn> @Reinhilde! What are the choices? I have a RISCVI32 processor
<jrtc27> ISA means nothing
<jrtc27> what matters is what the interface on your cache is and what the interface on your memory is
<jrtc27> AMBA, AXI, TileLink, Avalon, Wishbone, ...
<jrtc27> many mostly-equivalent options to choose from for an interconnect
<jrtc27> and whether you have DDR to talk to, SRAM, BRAM, etc will dictate what you put at one end
<jrtc27> or if you want a TCM you can directly connect your cache to your memory
<jrtc27> there is no answer to the question, just more questions
<kaaliakahn> @jrtc27, there is DDR to talk to
<jrtc27> are you writing the memory controller (probably not) or reusing some third-party/vendor IP?
<kaaliakahn> reusing 3rd party vendor
<jrtc27> so then the interface you need is whatever that uses
<kaaliakahn> @jrtc27 any pointers to open source memory controller for RISCV that interface with DDR
<jrtc27> idk, I'm not a hardware engineer, I'd just be googling like you
<jrtc27> maybe opentitan has something, maybe zip has something
<jrtc27> DDR generation is also going to be rather important though
<jrtc27> DDR2 and DDR5 are quite different
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<kaaliakahn> @jrtc27 Thanks so much
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<kaaliakahn> hi
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