sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Backup if libera.chat and freenode fall over: irc.oftc.net
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<carado> actually something pretty weird is happening with riscv-sifive-elf-objdump
<carado> with https://carado.moe/up/bd90c877-t.elf , i get endian reversal on instructions, and all the instructions are kept the same except for one which is now float ? https://carado.moe/up/8656d191-t.txt
<carado> this happens when i extract the code from the elf with objcopy
<carado> it's probly the disassembly from the elf that is correct and not from the raw binary, given that i don't have floating instructions in my code (which is a simple _start with a single assignment to a pointer)
<jrtc27> I assume -m riscv is defaulting to 32-bit not 64-bit
<jrtc27> as the compressed fsw instruction for RV32 gets reclaimed for compressed sd for RV64
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<seds> I am confused with the mcycle and mcycleh different in riscv 32 bit. I wonder how can I get the current clock count with these
<seds> seems that mcycle gives me a signed value sometimes
<sorear> mcycleh:mcycle is a 64 bit counter. there is no signed or unsigned here, you have to concatenate the bits
<seds> aha
<seds> makes sense now
<sorear> regarding reading the value, there's a code sample in the user spec in the counters section "The following code sequence will read a valid 64-bit cycle counter value into x3:x2,"
<seds> sorear: is this in the privilege doc?
<sorear> seds: no, "user spec"
<sorear> the user spec tells you how to read cycle and cycleh but mcycle and mcycleh work in exactly the same way
<seds> oh right, found the document! was checking on the wrong one
<sorear> also "rdcycle" is a funny way of writing "csrr cycle"
<seds> neat
<seds> thanks sorear, found the snippet you mentioned!
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