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<davidlt>
dlan, it works, because the errata workaround was added to OpenSBI
<davidlt>
dlan, if you have a modern CPU and you can give 8 physical cores to QEMU it will be faster than a hardware
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<davidlt>
I have some 8C / 32GB QEMU VMs just for some pacakges
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<dlan>
davidlt: ya, I've already set max 8 core, and give 20GB ram, put all compiling in tmpfs, still feel slow. take glibc-11.1.0 for example in unleashed vs qemu, it's 42min vs 2hour27min
<dlan>
cpu is E5-2680 v2 @2.8GHz (boost to 3.6G)
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<davidlt>
dlan, that's an old CPU :)
<davidlt>
those were quite nice a long time ago, but they are approaching a decade already
<Sos>
hmmm, Nezha board makers sent out a prebuilt image of debian
<Sos>
vai mega.nz
<Sos>
is there any legit place i can obtain any kind of prebuit system for RISC-V
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<choozy>
Sos, are you looking for a SBC or something else?
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<TwoNotes>
What is the difference between a "Supervisor Software Interrupt" (MIE bit 1) and an "Environment call from S mode" (mcause value 9)?
<jrtc27>
one is an ecall, a sychronous exception, the other is a software interrupt, an asynchronous interrupt
<dh`>
a software interrupt happens when that interrupt bit gets set, a call is when you execute the call instruction
<jrtc27>
(see mip.SSIP)
<sorear>
“software interrupt” in riscvthink means an inter-processor interrupt, not a system call like other arches
<TwoNotes>
Ah, ok. Not the same thing at all
<TwoNotes>
But both are considered "LOCAL", right? Specific to one hart
<sorear>
not sure “LOCAL” is a spec concept but by time you’re thinking about mcause, you’ve committed to take a trap on a hart
<TwoNotes>
Got it. I did see the words "local" and "global" in there somewhere. I think "global" is for PLIC interrupts
<TwoNotes>
But Vectored Mode seems to only apply to the mcause codes with the high bit set
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<TwoNotes>
I have to do my own vector for the others
<sorear>
it’s not really intended for general use, only for microcontrollers that can handle some interrupts without saving all registers
<sorear>
are you looking at soc docs? the sifive stuff uses local/global to describe incoming interrupt wires in the way you describe
<TwoNotes>
I have the specific U54 and U74 docs, as well as the ISA specs.
<TwoNotes>
I am writing to U54 right now, as that is what QEMU supports
<TwoNotes>
sorear do you mean that vectored mode is really for the smaller embedded applications?
<sorear>
yes
<TwoNotes>
ok. Since I need to do my own vectoring for the other half, I might as well treat them ll the same way
<TwoNotes>
Easier to debug
<sorear>
let’s start by pointing out you CAN’T use it (without even more jumps) if your image is larger than 1MB
<TwoNotes>
hm why?
<sorear>
JAL range
<TwoNotes>
So the hardware vectoring does the equivilant to a JAL?
<sorear>
no, the hardware vectoring drops you in a 4 byte region and the only thing you can fit there is a JAL
<sorear>
really should not use it without a specific reason
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<TwoNotes>
Oh, I see. That explains something. The vector table is not a tablle of addresses of routines, it actually is the start of a bunch of tiny routines
<TwoNotes>
So I am better off doing it myself, with a vector of real addresses that I fetch from
<jrtc27>
vectored also relies on you knowing the max interrupt number you'll ever see
<jrtc27>
ie that the privileged spec isn't going to add any extras, or your platform doesn't add custom ones
<jrtc27>
otherwise it'll jump past the end of your list of trampolines
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<TwoNotes>
I include a max range check
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