sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Backup if libera.chat and freenode fall over: irc.oftc.net
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<davidlt> dlan, it works, because the errata workaround was added to OpenSBI
<davidlt> dlan, if you have a modern CPU and you can give 8 physical cores to QEMU it will be faster than a hardware
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<davidlt> I have some 8C / 32GB QEMU VMs just for some pacakges
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<dlan> davidlt: ya, I've already set max 8 core, and give 20GB ram, put all compiling in tmpfs, still feel slow. take glibc-11.1.0 for example in unleashed vs qemu, it's 42min vs 2hour27min
<dlan> cpu is E5-2680 v2 @2.8GHz (boost to 3.6G)
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<davidlt> dlan, that's an old CPU :)
<davidlt> those were quite nice a long time ago, but they are approaching a decade already
<Sos> hmmm, Nezha board makers sent out a prebuilt image of debian
<Sos> vai mega.nz
<Sos> is there any legit place i can obtain any kind of prebuit system for RISC-V
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<choozy> Sos, are you looking for a SBC or something else?
<Sos> i'm getting one
<davidlt> You distro images for this SBC?
<Sos> but i don't trust the ssystem image they sent me
<Sos> via mega.nz link
<Sos> davidlt, yeah
<Sos> would prefferably not build one myself from source
<davidlt> I don't have one thus don't plan to make Fedora/RISCV available on it yet
<davidlt> not sure about others, but didn't hear much yet
<wigyori_> Sos: i'd think porting anything to this board other than what they provide isn't ready yet
<wigyori_> mine is also on the shipping ship, i'll look to get some level of openwrt support to it
<davidlt> there is nothing upstream about this SoC yet too, which complicates things
<Sos> wigyori_ i could compile some drivers and stuff myself, figured i'd have to do as much
<davidlt> Especially since D1 has also non-compliant things
<davidlt> e.g. most like V (vectors) will not be supported by distributions
<wigyori_> davidlt: i saw some (non-mergeable) patches around stmmac, but haven't looked any further yet
<davidlt> Alibaba/T-HEAD implemented 0.7.1 (not frozen, not ratified, not compatible with the final specification)
<Sos> yeah the V is wonky
<wigyori_> yep
<davidlt> They also have some DMA bits that use reserved PTE bits, which is against the standard
<davidlt> The chip can run in RISC-V compliant mode IIUC, but that will have some impact I assume
<Sos> alright, but can i just take a distro for a different board, boot into tty, gather hardware IDs and compile drivers?
<Sos> i hope this thing have tty over com if the hdmni doesn't work
<davidlt> yeah, you can do various things
<davidlt> people usually just take vendor kernel and take debian, fedora, gentoo, whatever rootfs
<Sos> yes! that's what i need
<davidlt> the rest will depend on Alibaba/T-HEAD
<davidlt> they sent some patches, started discussions threads
<davidlt> probably months until something useful lands
<davidlt> welcome to early adopters life :)
<wigyori_> :)
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<Sos> yay
<Sos> yeah i knew what i'm getting into
<Sos> i want to help maintain some game libraries
<pabs3> Sos: you could just use debootstrap to install Debian riscv64
<pabs3> although, I guess your board probably needs a custom kernel
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<TwoNotes> What is the difference between a "Supervisor Software Interrupt" (MIE bit 1) and an "Environment call from S mode" (mcause value 9)?
<jrtc27> one is an ecall, a sychronous exception, the other is a software interrupt, an asynchronous interrupt
<dh`> a software interrupt happens when that interrupt bit gets set, a call is when you execute the call instruction
<jrtc27> (see mip.SSIP)
<sorear> “software interrupt” in riscvthink means an inter-processor interrupt, not a system call like other arches
<TwoNotes> Ah, ok. Not the same thing at all
<TwoNotes> But both are considered "LOCAL", right? Specific to one hart
<sorear> not sure “LOCAL” is a spec concept but by time you’re thinking about mcause, you’ve committed to take a trap on a hart
<TwoNotes> Got it. I did see the words "local" and "global" in there somewhere. I think "global" is for PLIC interrupts
<TwoNotes> But Vectored Mode seems to only apply to the mcause codes with the high bit set
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<TwoNotes> I have to do my own vector for the others
<sorear> it’s not really intended for general use, only for microcontrollers that can handle some interrupts without saving all registers
<sorear> are you looking at soc docs? the sifive stuff uses local/global to describe incoming interrupt wires in the way you describe
<TwoNotes> I have the specific U54 and U74 docs, as well as the ISA specs.
<TwoNotes> I am writing to U54 right now, as that is what QEMU supports
<TwoNotes> sorear do you mean that vectored mode is really for the smaller embedded applications?
<sorear> yes
<TwoNotes> ok. Since I need to do my own vectoring for the other half, I might as well treat them ll the same way
<TwoNotes> Easier to debug
<sorear> let’s start by pointing out you CAN’T use it (without even more jumps) if your image is larger than 1MB
<TwoNotes> hm why?
<sorear> JAL range
<TwoNotes> So the hardware vectoring does the equivilant to a JAL?
<sorear> no, the hardware vectoring drops you in a 4 byte region and the only thing you can fit there is a JAL
<sorear> really should not use it without a specific reason
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<TwoNotes> Oh, I see. That explains something. The vector table is not a tablle of addresses of routines, it actually is the start of a bunch of tiny routines
<TwoNotes> So I am better off doing it myself, with a vector of real addresses that I fetch from
<jrtc27> vectored also relies on you knowing the max interrupt number you'll ever see
<jrtc27> ie that the privileged spec isn't going to add any extras, or your platform doesn't add custom ones
<jrtc27> otherwise it'll jump past the end of your list of trampolines
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<TwoNotes> I include a max range check
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<Xav101> Does anyone here know if the RV32I integer computation instructions are signed or unsigned?
<Xav101> I'm assuming it's signed? The manual doesn't really seem to say though
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<geist> theyr'e generally neither, since 2s compliment means it works either way
<geist> signed vs unsigned kicks in for mul/divs
<geist> and obviously float stuff
<Xav101> cool
<geist> but add/sub/logical ops/etc dont care about sign vs unsigned
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