sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Backup if libera.chat and freenode fall over: irc.oftc.net
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* sorear waits for a non-bloomberg source
<solrize> true dat
<pabs3> last thing we need is more company mergers/acquisitions
<djdelorie> heh, congress was just working on legislation to prohibit swallowing up competition... I wonder if this is what they were thinking?
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<solrize> intel needs all the help it can get lol
<xentrac> hmm, I thought I was immune to embarrassing fanboy flutters and celebrity swooning, but I guess I'm not
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<GreaseMonkey> what would intel do with a buyout of sifive anyway
<GreaseMonkey> maybe they'd use it for the next generation of Intel ME
<GreaseMonkey> maybe they'd see what they're doing that'll make x86 go slightly better
<GreaseMonkey> i doubt they'd actually attempt to sell RISC-V silicon that wasn't part of their ecosystem
<GreaseMonkey> but there's a part of me which thinks that maybe they might for the mobile space and/or the embedded space
<sorear> have we considered the possibility that this is for Altera
<GreaseMonkey> good point
<rjek> Also to mop up everyone who abandons ARM if NVIDIA manage to buy it
<solrize> there was someone saying they figured intel wanted to clutter up the riscv market by introducing a lot of proprietary extensions to the isa
<sorear> all of these are things they can do without sifive
<leah2> yeah but when sifive makes good chips, why would you buy intels :p
<solrize> yeah i wonder if sifive has sth they want, or if they just want to stifle a competitor
<sorear> they're not competing in any meaningful sense
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<gordonDrogon> Embrace, extend, and extinguish
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<arnd> Intel is trying to establish a foundry business (building SoCs for other companies in their own fabs). They already announced that these chips would be able to use Intel's own CPU cores under license, as well as third-party Arm and RISC-V cores: https://www.intel.com/content/www/us/en/newsroom/news/idm-manufacturing-innovation-product-leadership.html
<arnd> Having RISC-V cores of their own fits nicely in that strategy
<sorear> not sure about the cost effectiveness
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<TwoNotes> WHy would I be getting an 'illegal instruction' exception on an 'mret' instrcution while in M-mode? (QEMU sifive_u54)
<sorear> not actually in m-mode? bad setting in mstatus?
<sorear> look at helper_mret in op_helper.c
<TwoNotes> I know I am in M mode because this is early in boot phase. Maybe I set MPP wrong. I am trying to drop to S mode
<sorear> hmm, qemu throws an illegal instruction if you don't have any PMP rules configured, pretty sure that's nonconformant but you need to do that anyway
<sorear> (PMP behavior in S-mode is default deny; if qemu didn't special case this, mret with the PMP unconfigured would result in an immediate instruction access fault taken from S-mode)
<TwoNotes> WHat is PMP? Is that a QEMU thing?
<sorear> physical memory protection, look it up in the privileged spec
<TwoNotes> Ok, I know that term
<TwoNotes> Looking at op_helper, it even requires the mepc value to be 8-byte aligned
<TwoNotes> Ooops no, I mean 4-byte
<jrtc27> there's some dodginess in QEMU's implementation of xEPC legalisation
<jrtc27> but if you do normal things it works
<jrtc27> it doesn't need to be 4-byte aligned if you have compressed instructions
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<TwoNotes> I see where it checks for PMP rules, but only if MPP is not M. I guess to make sure PMP has been set up *before* changing out of M mode.
<TwoNotes> Since I have just set MPP to 'S' on purpose, that would trigger the fault
* TwoNotes goes off to read the PMP chapter again
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