<palmer>
olofj: do you have a LMKL link? I can't actually find that patch posted
<olofj>
No, I can't spot it either, but it seems good to go.
<palmer>
OK
<palmer>
davidlt: any reason it's not posted?
<olofj>
D'oh, just noticed that you already sent in. Ah well, next -rc perhaps.
<palmer>
ya, well, I sent for tomorrow
<palmer>
but I already have some fixes
<palmer>
more worried about finding the patch...
<palmer>
I'm always a bit leery of picking up patches that weren't posted
<palmer>
davidlt isn't tab completing (and I don't understand matrix well enough to find the list of user names), does he have a different handle here?
<psydroid>
you can try @username
<palmer>
ya, still not tab completing
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<palmer>
OK, well, I posted David's patch
<palmer>
I'll take it if he doesn't say anything by the time it gets back to me
<olofj>
sgtm
<olofj>
thanks
<palmer>
OK
<palmer>
not sure why it didn't get posted, David is usually pretty good about that sort of thing
<TwoNotes>
sorear, were you referring to qemu-trace-stap?
<sorear>
No, I'm referring to -D
<TwoNotes>
The output logfile option?
<sorear>
-d cpu,exec,int -singlestep etc been a while
<TwoNotes>
Ah I see. That looks useful. Especially as I am trying to debug my own interrupt handler
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<TwoNotes>
sorear, it just ocurred to me that the sifive_u has 5 harts, and hart zero is an E51, which I think lacks S mode and an MMU. no?
<sorear>
it lacks S-mode, but that should mean that attempting to set mstatus.MPP to 01 fails then (it will set MPP to a different valid mode instead)
<sorear>
although that doesn't seem to be implemented in write_mstatus, so maybe
<sorear>
yeah I think that's what you're hitting. qemu bug
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<TwoNotes>
But that might explain why I get illegal instruction trying to write to stvec
<TwoNotes>
I will play with the QEMU options to change the cpu configuration
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<TwoNotes>
Using the QEMU 'cpu 1' command to change which cpu it runs on DOES give different behavior, so there may be somehting in this
<xentrac>
ooh
<xentrac>
sounds promising
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<TwoNotes>
Ah, now I get a store access early in the S code where it tries to push registers on the stack. The SP is pointing to a place that SHOULD be writable in S mode, but isn't. SO I messed up PMP or MMU. This I can deal with.
<TwoNotes>
If I had just written this in C or Rust I might have avoided all this fun. :)
<TwoNotes>
But the point is to learn the grittystuff
<sorear>
access errors are PMP, page faults are MMU
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<TwoNotes>
This is type 7, access fault.
<TwoNotes>
Ok, so its PMP. The coding for that is very complex
<TwoNotes>
For example, if A=01 (TOR) does the setting of X, W, and R matter?
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<geist>
curious: what are you booing on? qemu?
<geist>
if so, which machine are you telling it to emulate?
<TwoNotes>
Yes qeumu, sifive_u, selecting cpu=1 to get (I think) an U54
<geist>
right. okay. sorry if you already covered it but you're explicitly not using the opensbi thing to get your code into S mode?
<geist>
fine if that's your purpose, just wanted to make sure you knew about it in case you werent interested in all the machine mode -> s mode bounce stuff
<geist>
since normally the opensbi code handles all of that, including not handing you HART 0 (the m mode only one) and only giving you boot control of one of the S mode cpus until you ask for me
<geist>
more
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<TwoNotes>
No, I am doing this bare hardware, not using OpenSBI.
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<TwoNotes>
I was disconnected 18 mins ago.
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<TwoNotes>
geist, where might I find the opensbi code that does this (force hart ID) for risc-v? ALl I have found so far is the opensbi top interface spec, not how it actually works
<geist>
in general my previous tracing of opensbi was that it traps all the cpus that have started (probably started all simultaneously) and only allows one through, based on a combination of features mask (ie, not HART 0 on real sifive hardware) and a hardware lottery (atomic variable that the other ones roll, first one to get the atomic wins)
<geist>
then it passes one core through to supervisor, and if the supervisor OS wants more it makes SBI calls to boot additional harts, which then SBI just releases from M mode, since it had previously trapped them
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<geist>
and hart 0 in particular (the M mode one) i think just sits there forever. i'm not sure it has a specific job in opensbi
<TwoNotes>
Yes, I am wondering how it does that. The way I read the specs, all harts boot at once, and follow the same logic. I suppose I could read the hartid (it is in a CSR) and do nothing if it is zero. Now, to make QEMU and GDB cooperate in this ...
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<TwoNotes>
Maybe this is what the QEMU monitor command "cpu N" is for
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<geist>
that just switches which one subsequent info commands work with
<geist>
like, say 'info registers'
<geist>
it doesn't change how it emulates it, or anything
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