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<Wanda[cis]>
okay. I think I can now just compute the BSCAN register for everything up to spartan6 and virtex6 without much pain.
<Wanda[cis]>
* BSCAN register order for everything
<Wanda[cis]>
virtex7, however, is uhhhh.
<Wanda[cis]>
so starting with virtex5 the boundary scan register contains a bunch of dummy bits between IO columns, prooooobably for pipelining reasons (presumably routing the JTAG chain all the way back down after every IO column would otherwise fail timing or something)
<Wanda[cis]>
for virtex5 and virtex6, the amount of dummy bits is easy to compute (it's 1 + <device height in clock regions> before each column)
<Wanda[cis]>
for virtex7, it gets quite complex and I haven't quite figured it out yet for all cases