<Wanda[cis]>
... okay I think I understand Laguna on Versal devices now
<Wanda[cis]>
so. xcvp1902. the funny super-large device with 4 die in mirror-square arrangement.
<Wanda[cis]>
the Laguna structure only makes sense if the devices actually are mirrored
<Wanda[cis]>
what the how the.
<Wanda[cis]>
can you like. just use a lithography mask the other way around or do you actually need to produce a separate mirror version
<Wanda[cis]>
I'm so confused
<Wanda[cis]>
or... just put two die upside-down on the interposer? that doesn't sound like a thing that can be done
<azonenberg>
Wanda[cis]: mask upside down: no. they have all kinds of things with phase shfiting and AR coating etc that i think would only work one way
<azonenberg>
but most importantly is you dont want to move the mask around in the tool between exposures
<azonenberg>
multiple mirrored dies on a reticle is plausible
<azonenberg>
but that would be a massive mask
whitequark[cis] has joined #prjcombine
<whitequark[cis]>
i imagine it's cheaper than like... P&Ring it four times?
<Wanda[cis]>
I mean you don't need to re-P&R it, you just need to flip the P&R result?
<azonenberg>
yeah
<azonenberg>
the mirrored layout will be equally manufacturable and pass drc
<azonenberg>
90 deg rotations, not so
<azonenberg>
most fabs require e.g. poly to all be oriented along one access in modern nodes
<Wanda[cis]>
I see, thanks
<Wanda[cis]>
alright. so. ultrascale.
<Wanda[cis]>
looking at the fpga geometry is fun and all but the main point is bitstream reversing
<Wanda[cis]>
unfortunately vivado is much stricter about netlist validity than ISE or xact and I cannot just create completely garbage routes that go nowhere, complicating interconnect reversing
<Wanda[cis]>
so I'd like to try out a new approach
<Wanda[cis]>
which is actually fuzzing-based as opposed to just calling it fuzzing because for some reason everyone calls FPGA reversing fuzzing no matter how it works
<Wanda[cis]>
and also I'd like to try it out on some smaller devices first before dealing with painfully slow vivado and painfully large ultrascale
<Wanda[cis]>
the good news is that the planned approach relies only on observation, not control of the routing, so it's going to be applicable to way more toolchains (since few of them let you control routing in detail)
<Wanda[cis]>
so, next target: icecube and ice65.
<Wanda[cis]>
... so do I emit Verilog or EDIF
<Wanda[cis]>
probably EDIF just for less processing on icecube side but ughhhhh this is annoying