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* cr1901 wants a New Lattice Smell car tree
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<Wanda[cis]> ohhh there's a new Vivado and it has spartanuplus devices
<Wanda[cis]> I wonder how much it's going to break my geometry extraction code
<Wanda[cis]> oh only up to su35p; no XP5IO for me
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<Wanda[cis]> huh.
<Wanda[cis]> as for "platform management controler", apparently the configuration center grew an AXI bus
<Wanda[cis]> (with the FPGA fabric being the requester)
<Wanda[cis]> it has also been renamed from "CONFIG_SITE" to "CSEC_SITE"
<Wanda[cis]> so there's a good chance this is some "secure element" bullshit going on?
<Wanda[cis]> no other new internal pins on that thing, just an AXI bus.
<Wanda[cis]> also "Lassen" is this a codename for this thing
<Wanda[cis]> huh. extra-large HDIO banks with 42 pins instead of 24.
<Wanda[cis]> I miscounted, 84 pins
<Wanda[cis]> ... and one of the extra-large HDIO banks even owns a CMT? huh.
<Wanda[cis]> crazy shit
<Wanda[cis]> like catgirls and doggirls living together
<Wanda[cis]> also surprising absolutely noone, su35p/su25p/su10p are the same die
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<Wanda[cis]> ... okay the banks do have 42 pins, there are just twice as many of them per clock region
<Wanda[cis]> oh. and it uses HDIO as the config bank.
<Wanda[cis]> how obscene.
<Wanda[cis]> ohh also the configuration interface is different?
<Wanda[cis]> it seems they removed parallel flash configuration
<Wanda[cis]> and added some new octal SPI mode ... which happens to have ECC? wtf is this
<Wanda[cis]> okay I have beaten the geometry extractor into submission
<Wanda[cis]> ... let's see if I broke anything else
<jn> at this point, i wouldn't be surprised if the SPI contoller also had DDR
<jn> i've seen it in flash datasheets
<Wanda[cis]> yeah me neither
<Wanda[cis]> but it's hard to know from just a pin list
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<cr1901> Can't wait for hexadec-SPI