#prjcombine on 2024-12-16 — irc logs at libera.irclog.whitequark.org

2024-11-12 16:41 ChanServ changed the topic of #prjcombine to: repo: https://github.com/prjunnamed/prjcombine/ | docs: https://prjunnamed.github.io/prjcombine/ | logs: https://libera.irclog.whitequark.org/prjcombine/

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17:02 <Wanda[cis]> okay, now that I think of it, I'm still missing a kinda important thing for xilinx, and that is boundary scan register order

17:02 <Wanda[cis]> I should just sit down and deal with that

17:02 <Wanda[cis]> not getting any INTESTing done without that

17:04 <Wanda[cis]> in related question

17:04 <Wanda[cis]> does anyone know wtf is the story with siliconblue and JTAG?

17:05 <Wanda[cis]> ice65 seems to have a proper JTAG port, but no documentation for it and no BSDL files; ice40 somehow seems to have TRST_B but no other JTAG pins in some packages and I have no idea what's going on

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