<Wanda[cis]>
for many devices, Vivado has _CIV/_SE/_LR variants, which appear to have an identical grid to the base device
<Wanda[cis]>
at least the _CIV devices have a different IDCODE, though
<Wanda[cis]>
wtf is this about
<Wanda[cis]>
the CIV devices appear to have software-limitted transceiver performance, and I found some vague information about this being about some chinese export control bullshit
<Wanda[cis]>
for SE I found an even more vague information about being "select edition"
<Wanda[cis]>
and LR is... no information
<Wanda[cis]>
(it appears to be new in this version, and only present for zu1eg, while _SE applies to a bunch of u+ and versal devices)
<Wanda[cis]>
I continue to be amazed by the trashfire that is versal
<Wanda[cis]>
they have like 3 different generations of AI engines, 2 generations of NOC tiles, 4 or so generations of DDR memory controllers, 3 generations of the ARM complex
<Wanda[cis]>
and it seems that whenever they create a new device, they just roll a random version of each; you'd expect them to use the newest rev of the AI engines on a new part with NOC2, but for some reason they stuffed the gen1 AI there
<Wanda[cis]>
oh, and also like 4 kinds of transceivers
<Wanda[cis]>
at least 5 different PCIE cores
<Wanda[cis]>
maybe their AI engines told them to do it
<mupuf>
Wanda[cis]: maybe this is a way to upsell current customers who have ready-made designs onto newer chips?
<mupuf>
Or they are really committed to A0 customer readiness
<mupuf>
Not sure what's the margins for FPGA vendors...
<mupuf>
Can't be so good given the current refresh cycles, but can't be so bad either given how big to he companies are and how dirt-cheap the nodes they are using are for volume parts are
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