klange changed the topic of #osdev to: Operating System Development || Don't ask to ask---just ask! || For 3+ LoC, use a pastebin (for example https://gist.github.com/) || Stats + Old logs: http://osdev-logs.qzx.com New Logs: https://libera.irclog.whitequark.org/osdev || Visit https://wiki.osdev.org and https://forum.osdev.org || Books: https://wiki.osdev.org/Books
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<moon-child> x86 now guarantees aligned 16-byte sse accesses are atomic. Does anyone know if arm/neon makes the same guarantee?
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<heat> google benchmark detected my qemu tcg's frequency at 62.5369 MHz lol
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<geist> that seems a little low but then of course who knows how that maps to it's benchmark
<heat> yeah i dunno, its pretty accurate on real hw, but this isn't real ofc
<heat> device tree interrupts suck ass
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<heat> the schema is magically defined by whatever intc is at the other end, and it's not even described in the device tree itself
<heat> a device tree is legitimately not self-describing and this pisses me off
<geist> word.
<heat> it *almost* makes ACPI look good, if it didn't require executable bytecode
<moon-child> oh right arm has stp/ldp
<moon-child> ...but are those atomic?
<heat> geist, are socs with multiple intc all chained together (or not chained at all) any sort of common in the ARM world?
<moon-child> https://reviews.llvm.org/D67485?id=219866 sez armv8.4-a and later
<bslsk05> ​reviews.llvm.org: ⚙ D67485 AArch64: use ldp/stp for atomic & volatile 128-bit where appropriate.
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<zid> Nice to see the fact AMD setups are brand new and the bios software is immature isn't having repercussions like on fire cpus and dead mobos.
<zid> Oh wait nevermind :p
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<heat> zid, hm?
<heat> what did I miss
<klange> oof
<zid> GN finally posted their findings vid on it
<heat> ew
<heat> are zen4 LGA?
<zid> am5 is lga yea
<zid> so is am4
<zid> err no just am5?
<zid> *checks*
<heat> hm didn't am4 have the pins on the socket?
<heat> erm, cpu
<zid> yea just am5
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<heat> gog gogzilla
<gog> hi
<zid> gog
<gog> hi
<zid> did you look at my link
<gog> when
<zid> I tried to show you it all day yesterday I can repost
<heat> gog i sent u my penis did you see it yet please respond haha
<gog> haha yes'
<gog> heat: blocked and reported
<zid> heat: omg is this child porn!?
<zid> Why is it so small
<heat> 😭😭😭
<mrvn> Hehe, die Edeka Schmelzkaesescheiben (also die dinger die voll processed und mit chemie sind, sind "Ohne Gentechnik".
<CalculusCats> e
<zid> ^
<sham1> Nickname checks out
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<awita> Do I need to setup a TSS if I only want to implement kernel mode tasks?
<zid> if you want to take IRQs yea
<awita> Do you mean handle IRQs from the tasks?
<zid> From the.. interrupt controller
<awita> But I already handle IRQs without any task
<zid> Then you'll take IRQs on your regular kernel stack I guess, should work with -mno-redzone
<awita> It's for x86 only, not x64
<zid> I'm not sure how you managed to set that up though
<awita> should have said that before sorry
<heat> no you don't need a TSS if you're ring0 only
<zid> can you control whether tss gets used for ring0 -> ring0?
<zid> or do you just always not use it
<heat> at least in x86_64 you can (with interrupt stacks), not sure about 32-bit
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<zid> can't find where it says you can, oh well, I'm not that bothered, distracting me from my audiobook :P
<heat> i don't find a particular use for irq stacks atm, i just handle them in the kernel's stack
<heat> it should be Fine(tm)
<heat> s/kernel's stack/thread's kernel stack/
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<mrvn> I would think the cpu always has to check the TSS in case you do want to set up an IRQ stack. Surprises me that you can not set a TSS and IRQs don't tripple fault.
<mrvn> You do need the TSS to handle double fault.
<mrvn> e.g. a task uses too much stack.
<mrvn> awita: are you sure you don't have some TSS set up from your bootloader and it just happens that still works?
<awita> Maybe. How would I check that?
<awita> https://github.com/Xayiide/ChamacOS This is the code in case it's useful
<bslsk05> ​Xayiide/ChamacOS - Proyecto de fin de máster: sistema operativo sencillo de programación fácil (0 forks/0 stargazers/GPL-3.0)
<mrvn> awita: load the null descriptor into the TSS?
<mrvn> I would just make a proper TSS, implement and test the double fault handler.
<awita> But IRQs don't work without setting up a TSS?
<Mutabah> TSS is needed for going from user to kernel mode
<awita> Yes but I don't have user mode yet
<Mutabah> don't technically need it when there's no level change
<Mutabah> mrvn: The CPU only queries the TSS if its needed (changing to a higher-priv ring, or an IST was specified)
<awita> When I come back home I'll check loading a NULL descriptor into the TSS and seeing what happens
<awita> If I'm not using it (as I think I am) nothing should break
<awita> Thank you
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