klange changed the topic of #osdev to: Operating System Development || Don't ask to ask---just ask! || For 3+ LoC, use a pastebin (for example https://gist.github.com/) || Stats + Old logs: http://osdev-logs.qzx.com New Logs: https://libera.irclog.whitequark.org/osdev || Visit https://wiki.osdev.org and https://forum.osdev.org || Books: https://wiki.osdev.org/Books
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<memdudess> so in that sense mrvn was even kind of right, if the memory uploaded to i-cache is marked read-only in that phase when channel changing is also hidden in the pci bases, then one is behind MPU latch and can not sense stuff. However there are decoupling capacitors for the power-lines, technically when there is no power on the circuit there is also
<memdudess> nothing that charges them. And this latch can probably be bypassed, but this is allready very complex , cause it requires to anticipate the compression.
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<memdudess> It's likely that interrupt lines flag/pin in the memory address is accidentaly stepped on like a landmine, and it discards everything, can be programmed so, so this pipeline would end up being fairly secure. You would need to have a very very fast interface to corrupt the interrupt line backing memory allready.
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<devcpu> jeez, what is this gibberish?
<klange> Sometimes he has days where I think he's actually got a point to make and is coherent enough to get close to it, but most of it is just gibberish.
<clever> klange: i checked, and he is still on the exact same nickserv acct as a few days ago
<clever> so an acct ban may help
<klange> I did apply an extban for that.
<clever> ah, i see it now, perfect
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<allowtolaugh> this is getting hilarious how big nutters you are, so if the test of the mpu is on the memory controller stack broadcasted to dma controller which forwards to memory controller in the asic early test, say latency is 100ps to access a word in one pipeline stage for all the rw scanout and rd probably it is slihtly more, you need to do 200times faster
<allowtolaugh> allready to corrupt flop, but you can not do 200times faster unless you are on photonics, if you were running on the fast pipeline allready, you are hilarious humans.
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<GeDaMo> Are they registering new accounts to get around the bans?
<clever> GeDaMo: seems so
<kazinsal> yep
<kazinsal> there's no way to get rid of someone on an IRC server
<kazinsal> so we just have to hope he gets bored/stops combining antipsychotics with alcohol
<clever> kazinsal: the only method ive seen really work, was to falsely report to their ISP that they are spreading a virus, and they they just loose internet, lol
<clever> but false reports could be even more troublesome...
<kazinsal> no idea what their ISP even is, or any details whatsoever, since they've been using random compromised IP addresses as proxies for years
<clever> yeah, thats the other issue
<Mutabah> Iirc long ago someone managed to make contact with a family member who helped for a while...
<Mutabah> But not sure if that avenue is still available
<kazinsal> "your relative is abusing people on our IRC channel" is probably fairly low on most people's things-to-give-a-shit-about list I suspect
<Mutabah> "your relative is off his meds" is more reasonable
<kazinsal> I mean I'm pretty sure he's also threatened to murder most of us at least a dozen times each by now as well
<kazinsal> And I'm going to assume that Estonian law does not consider that to be kosher
<Mutabah> Oh, he did just that (with some rather vivid imagery) via PM 30s ago
<kazinsal> I turned on caller-ID for PMs after K mentioned it was a thing
<Mutabah> Maybe should turn it on, but meh
<bslsk05> ​libera.chat: User Modes | Libera Chat
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<mandelbrotA> devcpu: I really advise you to not interact with me, cause due to your violations and totally senseless talks and your crap os's copied from BSD i.e no brain interactions involved, you gonna all end up in mental insitution and there is no one among you who will come out from there alive at least the meds you caused me to take , here is no strong
<mandelbrotA> man enough to handle those. So if electronic components have no load, where would the power suppose to come, it comes from capacitors on motherboard, are you born yestirday or what? Memory passthrough you know charges those, but if there ain't also correct signal, than those gonna be passed also corruptedly, that is how rowhammer works or does not
<mandelbrotA> it, rowhammer is little less sane hack, there is easier one of course, but good demo still?
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<dzwdz> it's not possible to /ignore based on the account name, right?
<clever> dzwdz: dont think so, and its hard when the acct keeps changing
<dzwdz> he only changes accounts after bans
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<geist> he changes sometimes anyway
<dzwdz> still, better than nothing
<geist> there's really nothing that can be done, since he just keeps re-registering. it's not that he's trying to troll us, he's simply mentally ill and will just keep coming back
<geist> has been for years
<hbag> jesus what did i wake up to
<GeDaMo> "Normal service will be resumed as soon as we are sure what is normal anyway" :P
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<Affliction> dzwdz: depends on your client
<Affliction> with appropriate ircv3 support, it's technically possible, though it looks like mine doesn't
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<randiosum> And if you kind of like look at this, of course you can read the patent and read out the details, and i have them bookmarked too, but all the grates in digital asics are CMOS today, that means complementary metal oxide semiconductor, automatically that means VCC and VDD lines, so most logical of course is two powerline capacitors, where 0 is
<randiosum> directed to one branch and 1 to another, can me different but i always bet on this formation., it's quite easy to manipulate, but the defense is pretty solid when done right, only very very fast interfaces could do something about it.
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<[itchyjunk]> Not trying to brag or anything but i'll just leave this here =) https://bpa.st/5VRA
<bslsk05> ​bpa.st: View paste 5VRA
<j`ey> [itchyjunk]: show off!
<jimbzy> Hey, [itchyjunk]! How goes the maths?
<[itchyjunk]> hello jimbzy. it goes poorly but i am almost done, last semester
<jimbzy> Boo/yay
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<[itchyjunk]> what kind of math have you been up to lately?
<jimbzy> Very little, actually. I have a discrete maths class coming up in a few weeks, though
<clever> ive been looking into debayer lately
<[itchyjunk]> ah fun
<clever> realized that i could maybe abuse the texture lookup unit in a 3d core for debayer
<clever> but unpacking the data is still a bandwidth intensive step
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<jimbzy> I finished up multivariate calculus last semester and decided to try something different.
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<[itchyjunk]> yes its different and one of the first places where you start getting into proofs
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<NieDzejkob> [itchyjunk]: huh, am I missing something? The way I'm reading this, the add x3 instructions are dead stores due to the following jal?
<GeDaMo> NieDzejkob: [itchyjunk]'s program doesn't actually work :P
<[itchyjunk]> yes i misunderstood jal :(
<[itchyjunk]> premature ceelbration
<[itchyjunk]> well, my old code doesn't work. my new one looks like this : https://bpa.st/VN2Q
<bslsk05> ​bpa.st: View paste VN2Q
<GeDaMo> Does it work? :P
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<[itchyjunk]> well, it does store the minimum value of the two in a register. just need a definition of "work" to fit that
<GeDaMo> That's the spirit! Redefine the problem so what you already have is the solution :P
<NieDzejkob> why the jump to a label just after the jump? ;)
<NieDzejkob> hmm, how about add x12, x0, x10 / blt x10, x11, end / add x12, x0, x11 / end:
<bslsk05> ​www.cs.cornell.edu: RISC-V Interpreter
<NieDzejkob> my mind is enough to test this, I don't need a pesky interpreter
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* NieDzejkob has never written a line of RISC-V asm before
<[itchyjunk]> I think what you suggest would work
<GeDaMo> I helped somebody a while back with what I thought was MIPS, turned out to be RISC-V but it's similar enough that my code worked :P
<[itchyjunk]> So pseudo codes aren't actually functions.. so what are they?
<[itchyjunk]> i assume someone will make a `jump label` pseudo op code that does `beq x0, x0, label` or somesuch
<GeDaMo> They're just aliases for actual instructions
<GeDaMo> I think in MIPS, that's usually just b label
<GeDaMo> Looks like RISC-V has j offset
<NieDzejkob> they're like macros
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<geist> yah also the assembler is generally free to relax instructions so it can generally replace 32 bit instructions with 16 bit at will
<geist> (if compiling for .c variant)
<klys> 3.1415926535 8979323846 2643383279 50
<klys> 535 8 979 323 84 626 43 383
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<geist> das ist nümberwang!
<klys> =)
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<NieDzejkob> oh, so pi's now the topic? ok. my favorite pi fact is that pi with 42 decimal places ends at 69: 3.1415926535 8979323846 2643383279 5028841971 69
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<geist> huhuhu huhuhuhu 69
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<jimbzy> π ≈ 3 ≈ e
<jimbzy> I'm mathing!
<dude12312414> wait 'till you see that e^pi - pi = 20
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<geist> huh interesting. it's not exactly, but pretty close
<geist> didn't know that
<geist> well, now you know if you need to compute 20 to a few decimal places, here's a great trick!
<klange> e ^ (i * pi) = -1
<moon-child> cuz cos pi = -1
<moon-child> e ^ (ix + y) = cos x + sin y
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<teletups0> I was generally also little confusing the concepts, dma has no memory protection, i was talking about the idea for firmware to redirect into some of the interrupt causing memory lines, by allocating parts of the region for the burst to it, once the encoding is messed up very fast interfaces are needed to recover from it, interrupt presumambly is
<teletups0> called from the memory controller , so to corrupt that interrupt back off, highly fast line is needed, i.e the measure is fairly secure., so the powerlines are rather irrelevant cause you can than read the address , decode the inst, corrupt the interrupt and overwrite the address., and stale cache copies are also not recoverable i.e not memory
<teletups0> protected, but slightly different way to get a stale cache copy due to memory type handling, so in fact i was somewhat inconsistent due to pressure, but host bridge and dma can not access the memory in parallel, so it is going to be either one on the same channel
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