klange changed the topic of #osdev to: Operating System Development || Don't ask to ask---just ask! || For 3+ LoC, use a pastebin (for example https://gist.github.com/) || Stats + Old logs: http://osdev-logs.qzx.com New Logs: https://libera.irclog.whitequark.org/osdev || Visit https://wiki.osdev.org and https://forum.osdev.org || Books: https://wiki.osdev.org/Books
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<rainmodel> Bunch of std errors i got which i could not overcome on ios compiler, had to cross compile rust, i am getting very close cause only host is osx, limbo almost like wanted to compile crossly programs to ios from osx bootsrap.
<rainmodel> Well i am also tired about all this , the way i see you might also behaved more civil and not publicly trash me, every time you provoked the issues and did not perhaps made too much correct info available either, hence even though i do not know those people, some just interferred into our conflicts, it was getting abusively mad you know.
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<rainmodel> i do not know very much how cross compiling is done, but for some reason the ld tries to execute binary format of mach-o ith its cross toolkit on linux host, i also do not know what to make out of this tbh.
<rainmodel> it suddently redirected to binfmt misc from cross osx compile toolkit, but i suppose the correct way to to do the compilation in chroot of limbo
<rainmodel> I have cross compiled before, and i suppose it did not quite work so, but android arm64 and 32bit variants should be only elf, but this is allready cross container compilation what i do
<rainmodel> and that i perform for the first time, kvm solutions i am not so keened of
<rainmodel> i think we understand that general consensus would end up being, that this thing could be done whole lot better, to compile from ios for rusts targets from linux
<rainmodel> cause such setups i have done, i imagine not many could do very naturally, it's complex too much
<rainmodel> there are some intermediate ideas to have syscall glibc in elf somehow and just objcopy the binary to mach-o, but this is not what i would like the most either
<rainmodel> but my solution would be better, but currently no way to allocate time for this
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<rainmodel> technically i understand that it is all about getting the linker parameters right, but my linker line on usbip was roughly 4pages
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<rainmodel> I got so far cause of theos toolkit on linux, and it seems to support and is maintained to have such clang and LLVM from release-10, as a bingners repository on ios.
<rainmodel> that actually seems to compile from elf x86_64 to ios aarch64 mach-o
<rainmodel> i knew that those llvm people had it times back and always programmed it to have it
<rainmodel> but the LLVM is nowdays probably associated with apple
<rainmodel> and they do what they want to influence their position to be better
<rainmodel> sort of like endorse their products and produclines in sw and hw
<rainmodel> because i am a real programmer , i do not quite like this type, i am not real programmer, but random user, but i like real code
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<rainmodel> The same kit is being used for the ios side, that i did not have repository for, sileo can add that
<rainmodel> but procursurus or something along the lines have the sileo package, which you execute over ssh
<rainmodel> it is under /Applications/Sileo/Sileo.app
<rainmodel> and to jailbreak the device
<rainmodel> you just add some lines of libdimentio for the hw and ios identifiers
<bslsk05> ​Baw-Appie/KernBypass-Public - chroot based kernel level jailbreak detection bypass. (is fork /0 forks/0 stargazers/GPL-3.0)
<bslsk05> ​github.com: KernBypass-Public/libdimentio.c at master · Baw-Appie/KernBypass-Public · GitHub
<rainmodel> this file needs additional id's for new i-boot
<bslsk05> ​github.com: dimentio/libdimentio.c at main · 0x7ff/dimentio · GitHub
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<rainmodel> you get things the wrong way, it works in such kind:
<rainmodel> first you compile and sign the kern-bypass stuff
<rainmodel> then you add it to the start up, and then you run anything what you want
<rainmodel> it's just how to precede some options on the LLVM i actually never knew, llvm toolchain from theos, triggers one opetion which is not respected well
<rainmodel> i think there was a switch to not turn this into an error, and it should also compile the usbip rust codes
<rainmodel> by issuing something like this in sequence
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<rainmodel> export CXXFLAGS="-Wno-incompatible-sysroot -Wno-error=all -miphoneos-version-min=10"
<rainmodel> export LD_LIBRARY_PATH=/home/mart/theos/toolchain/linux/iphone/lib/:$LD_LIBRARY_PATH
<rainmodel> export PATH=/home/mart/theos/toolchain/linux/iphone/bin/:$PATH
<rainmodel> and in usbip directory, run such command:
<rainmodel> env RUST_LOG=info cargo run --example hid_keyboard --target=aarch64-apple-ios
<rainmodel> two other examples are even more interesting :)
<rainmodel> so those commands all required theos to be set up accoring to tutorials, and rustup to update to rust and cargo upstream
<rainmodel> and have the toolchain from theos to use an additional flag to allow unrecognized options to be warnings
<rainmodel> and maybe -arch arm64 should be switched to -arch aarch64 , do not quite remember that
<rainmodel> this would compile the binaries also for IOS, i suppose, that gets a remote port on both sides, server can be now also IOS, which serves it's libusb identifiers and logic to the linux
<sortie> Hello rainmodel
<rainmodel> from there you access a serial port gateway to usb
<sortie> Who are you talking to?
<rainmodel> and that would allow you to refresh the phone to any of the IMEI's and maybe secure the kernel or do something
<rainmodel> when someone never cared about his phone and got a new one and lost it permanently
<rainmodel> I do not like to do such work, but yes of course i knew about systems my own
<rainmodel> i used similar tools 15years ago to test them, and it worked
<sortie> rainmodel, you're spamming the channel with a whole bunch of stuff, and it's unclear how people can use the information or talk to you
<sortie> > /home/mart
<sortie> rainmodel, hey Mart!
<sortie> You should've said hello, it's been a while! How are you?
<zid> how the hell did you not notice who it was lol
<sortie> Estonia treating you well, rainmodel?
<rainmodel> Yeah i Don't know about estonia, i have been away for 1.5years.
<sortie> Ah where are you now?
<rainmodel> In cambodia, i sat there 6times, and was realesed with the best possible behavior.
<rainmodel> then i got more sanctions over my human rights, then i came out
<rainmodel> let them find another patience, i said i am not interested you silly maniacal pigs
<sortie> Cambodia, eh?
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<rainmodel> WHen they want to also raise up people or endorse who are not worth it and treat me like this, then go ahead with new patience, but i am gone from there
<rainmodel> patients
<rainmodel> i can go to europe and play couple of more years of table tennis
<rainmodel> cause i am freakin old now, but i loved that one
<sortie> Anyways nice to catch up with :)
<sortie> * with you
* Mutabah waves
<sortie> Now, I know you're very busy and have to go do some nice self care
<sortie> So catch you later one of these months rainmodel
rainmodel was kicked from #osdev by sortie [Come back next year]
<sortie> Always nice to see our regular spammers have made the journey to libera
<Mutabah> zid: You reach a point where you can identify someone by their "speech" patterns
<Mutabah> Some are easier than others
<zid> Agreed, and that guy is trivial
<Mutabah> been pretty quiet today (other than mart)
<sortie> Yeah I thought it was him but then got in doubt when he was mode coherent than usual and pasted commands related to osdev
<sortie> You know, he makes the ponder. I'm thinking he's got some serious traumatized issues. I think he needs to be seen and struggles to show the cool tech stuff he's doing, but has some severe attachment issues and has trouble reciprocating.
<sortie> Or something. Mart, I hope you learn to care about the people in your life. It starts with you feeling good about yourself
<zid> no he's just schizophrenic
<sortie> Whatever he is, he clearly has issues actually caring about us in this channel
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<bslsk05> ​twitter: <textfiles> The moment of stunned silence after someone suggested the ad copy. The two days of trying to come up with alternatives and failing. https://pbs.twimg.com/media/E9Zx4VBX0AEFJe0.jpg
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<vin> Can one estimate the max UPI link rate with the number of UPI links available? example intel 8280 has 3 links and gives 10.4 GT/s and 9242 has 4 but what would be it's transfer rate?
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<vin> Also is there a way to identify TLB size of a chip without acess to it?
<zid> google/
<vin> zid: no I tried, nothing shows up. For examole if you have acesss to the machine you can then get it from cpuid. I was looking for the tlb size of Xeon 9282 which I can't find anywhere
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<vin> can't find it for any chip for that matter
<zid> yea that's a pretty rare cpu
<vin> I suppose the intel ISA manual won't have it.
<zid> no you'd need the specific product one
<zid> or to ask intel
<vin> zid oh do each chip intel come with a manual?
<vin> *intel chip
<vin> I don't think so
<zid> nope
<zid> there may be manuals for the generation of chips though
<zid> which may have some tables
<bslsk05> ​en.wikichip.org: Cascade Lake - Microarchitectures - Intel - WikiChip
<vin> thanks GeDaMo that was helpful. So irrespective of the core count the tlb size is kept constant? Wouldn't it be better if the size increased with core count like l2/l3 does?
<GeDaMo> Is that not per core?
<vin> Oh I hope it is. Just 34 entries for 96 threads would be so bad
<GeDaMo> The block diagram makes it look like it's per core https://en.wikichip.org/w/images/e/ee/skylake_server_block_diagram.svg
<GeDaMo> The instruction TLB is attached to the icache at the top
<vin> yes you are right
<vin> GeDaMo: do you know if UPI interconnect rate (10.4 GT/s) is per link or total?
<GeDaMo> Sorry, no idea
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<vin> no worries, thanks
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<zid> per link
<gorgonical> Need a little ARM64 expertise: For a benchmark I need access to the PMU cycle counter in EL0. When running my kernel natively, I can enable via pmuserenr, pmcntenset, and pmcr. But if my kernel is being virtualized I get an undefined instruction error. AFAICT there's nothing in the manual that explains why this mrs, pmccntr_el0 is causing that exception. Anyone have a clue?
<gorgonical> I was having this problem with the kernel until I remembered to add that enabling code. But the hypervisor (should) be letting all the enabling code in the kernel through.
<zid> This is complete conjecture but it sounds like you need to enable some bit that makes it a vm exit
<gorgonical> It's supposed to actually allow access to rdtsc without a vm exit, really
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<ZetItUp_> that moment when you find out you've been passing throu the wrong data to your interrupt handler all along
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<Bitweasil> gorgonical, there are some SCRs related to that.
<Bitweasil> The hypervisor has to pass it through.
<Bitweasil> Take a look at cnthctl and cntkctl
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<heat> yo
<heat> does anyone know of any good x86 boards/SBCs to hack on?
<heat> preferably not too expensive
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<brynet> heat: pcengines apu boards aren't super expensive
<heat> Availability: expected ~ 2022
<heat> RIP
<heat> All I want is a decent board to tinker with. Do bring up work, osdev, etc
<heat> the obvious answer is the raspi for ARM64 of course
<heat> riscv64 seems lacking and x86 yeah... I haven't found a good relatively open board
<heat> I'm not sure if doing bring up work on a random board like that is feasible
<moon-child> I thought there was a somewhat prominent riscv board? Tho much more expensive than the equivalent (perf-wise) pi
<heat> yes there's an sifive riscv64 thing but it's wayy to expensive for a hobby-ish thing
<heat> at least for me that is
<heat> the idea with getting an arm64/riscv64 board would be to port my OS to it and do fun stuff there
<heat> the idea with getting an x86 board would be to do bring up work and then put my OS there, and have only my code run there, if you forget the intel FSP + intel ME stuff