klange changed the topic of #osdev to: Operating System Development || Don't ask to ask---just ask! || For 3+ LoC, use a pastebin (for example https://gist.github.com/) || Stats + Old logs: http://osdev-logs.qzx.com New Logs: https://libera.irclog.whitequark.org/osdev || Visit https://wiki.osdev.org and https://forum.osdev.org || Books: https://wiki.osdev.org/Books
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<pony> hi
<pony> what is a suitable piece of hardware to start out (osdev) on?
<pony> I am thinking perhaps ARM based
<vdamewood> Virtual hardware.
<Mutabah> I'd suggest qemu x86 just due to available examples
<Mutabah> that said... qemu riscv is also quite nice
<pony> ok :)
<vdamewood> Any of x86, RV and ARM are fine, though.
<pony> any recommendations with regards to my first question after I've gained some experience with virtual hardware?
<j`ey> rpi?
<pony> ok
<vdamewood> Anything but a Mac?
<pony> hehe
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<klange> vdamewood: heh, the dev who started the Asahi Linux project to bootstrap the M1 is a friend of mine (via a combination of locality and other IRC channels) and I was chatting during one of their live streams and someone asked when ToaruOS's m1 port was happening ;)
<j`ey> that someone was me :P
<klange> Small world, anyway the answer is _gods dammit man I haven't even bought one of the things yet_.
<klange> Need to get a less insane ARM target first, and then maybe I can convince marcan to help out with an M1 target.
<j`ey> he has enough on his plate with asahi :P
<klange> Some variety of aarch64 port is on the timeline for "after we at least have a USB stack", so it's a longs ways away anyway.
<j`ey> klange: im confused where is the main toarus code?
<bslsk05> ​github.com: ToaruOS · GitHub
<klange> https://github.com/klange/toaruos ← Under my user account, not the org
<bslsk05> ​klange/toaruos - A completely-from-scratch hobby operating system: bootloader, kernel, drivers, C library, and userspace including a composited graphical UI, dynamic linker, syntax-highlighting text editor, network stack, etc. (349 forks/3542 stargazers/NCSA)
<j`ey> wait, did you just delete the 32bit code?
<klange> basically
<klange> poke the last release tag if you want the old stuff, I don't think the new kernel will ever be backported
<j`ey> I just assumed you'd keep both
<klange> Nah, out with the old, in with the new!
<klange> Let git take care of the history.
<klange> Since it's a brand new kernel, as much as some code is just copy-pasted, it would be tricky to keep both codebases together in one repo. If it would be necessary to do a proper port back to x86-32 if that's what I wanted, but I don't, so *shrug*, onward and upward!
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<sahibatko> Hi, I am in the middle of writing an x86-64 UEFI app (bootloader), the spec (2.9) is quite nice to read, but I might have missed some details: It says in 2.3.4 the state "During boot services", but what is actually guaranteed after ExitBootServices call? Can the processor state be changed by that call?
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<gog> sahibatko: ExitBootServices() guarantees that firmware services are stopped, and afaik it doesn't affect any CPU state
<gog> it might clear RFLAGS.IF?
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<gog> it doesn't specify and i cba to test that lol
<sahibatko> right ... I will probably choose only to test the basic expected minimum sensible state (long mode, ia32-e paging) and then start from scratch, disabling interrupts as the first step
<j`ey> I think that's a good idea
<j`ey> assume nothing!
<sham1> Well you could always trust the spec, although checking might still be worth it
<sahibatko> Right, one should not ass-u-me, but still I have to believe that my hand-over-structure that is allocated durig boot services stays untouched. Is there really no word about these things?
<Mutabah> allocated memory should stay as-is
<sham1> I wonder how allocation within the bootloader/EFI application affects the received memory map. And mostly whether it'd be better to just receive it before doing a lot of allocations
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<gog> when you call ExitBootServices() you need to have the current memory map key and it has to match the one the firmware has or it'll fail
<gog> so it's better to get it just before leaving
<gog> it's a bit of a chicken-egg situation because allocating memory to store the map will alter the map key
<gog> what i'm moving to is i allocate a buffer 2x the size of the memory map at startup and use it repeatedly
<gog> it's overkill but guarantees you'll never have to allocate more space for it
<sahibatko> I determine the size every time and assume that one extra alloc takes max. 2 new entries (space + new type)
<gog> that works too
<sahibatko> though it makes me wonder if +2 is always OK :-D
<gog> because i don't think it'll ever split a block, it'll always grab from the base or the head
<gog> for ovmf it seems to always go top-to-bottom
<gog> can't speak for real metal implementations tho
<sahibatko> Actually, I have another question: in the GOP protocol (chapter 12.9) it says that the framebuffer is exposed for direct write, but is it possible to keep this for use after ExitBootServices? I mean, not the protocol, but the framebuffer at the same address
<gog> yes
<sahibatko> any special requirements or just map it and use it, Perhaps it can be used even before the "new" mapping? - I am asking because that will be the next piece of code to write :)
<gog> only the obvious, that you use its pixel format and pitch correctly
<gog> and also do check that it's not a Blt-only first
<sahibatko> nice
<sahibatko> right, those I already skipped during enumeration
<gog> also checking the memory map for its correct caching parameters
<gog> it might want to be set up for write combining
<gog> but i've only played with that a little, by no means an expert :
<gog> :p
<sahibatko> thanks - off for some coffee
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<bslsk05> ​twitter: <marcan42> I just found out that the M1 Mac Mini uses an MCDP2920 DisplayPort to HDMI converter chip. ␤ ␤ That chip has an embedded V186 CPU. Yes, as in x86. ␤ ␤ Intel found a way into M1 Macs.
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<clever> lol
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<dzwdz> so i'm reading up on the GDT and i'm a bit confused - should i just make it so both the ring 0 and ring 3 segments span the whole memory?
<dzwdz> the wiki seems to suggest that, but wouldn't that make it so ring3 can modify memory from ring0?
<sham1> Yes, but you can then use paging to limit the editable userspace memory
<dzwdz> ah
<moon-child> note in 64-bit mode the segments will span the whole memory no matter what you do
<dzwdz> so i won't have to mess with the GDT any further after setting up those 4 segments?
<moon-child> (except fs and gs)
<sham1> Well you need a GDT for TSS
<moon-child> dzwdz: you will need to mess with it when you implement thread-local storage, but not aside from that
<sham1> And IIRC you need some more of them for some SMP things
<dzwdz> aight, thanks
<dzwdz> and is the null segment just supposed to be filled with 0s?
<moon-child> you can just make the present bit 0, I think, but having done that no reason to put in effort to fill in the rest of it
<geist> j`ey: heh yeah saw that
<dzwdz> does it have any purpose?
<geist> the null segment? it's basically unused, because loading a 0 into any segment register is implicitly disabled
<geist> so the cpu will never actualy read the 0th entry in the GDT, hence it's just 8 bytes of whatever
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<Bitweasil> I thought a lot of stuff point the GDT pointer there, since you load indirectly... maybe?
<Bitweasil> There's some weird trick with GDT[0] I seem to recall.
<Bitweasil> been a while since I've stared at x86 "get to 64-bit" code though.
<geist> Bitweasil: yeah that's basically a trick to save 8 bytes, because the first entry is unused, you can put the gdt pointer (16 + 32) in it
<geist> since the cpu will never actually read from the first GDT entry, it's just 8 bytes you can do whatever you want with
<Bitweasil> *nods* I was pretty sure I'd seen that at some point or another.
<Bitweasil> lulz old Xeons.
<Bitweasil> I replaced a dual socket Westmere box with a 6th gen i5, it's about 70% the performance on a quarter the power.
<gog> is 6th haswell?
<gog> i loved my haswell
<kazinsal> skylake iirc
<gog> oh
<kazinsal> aka the last time intel managed to get an IPC improvement on 14nm
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<dzwdz> how do segment selectors work? the TSS page mentions that if i have tss in the 6th segment the selector == 0x28, but it doesn't explain why
<dzwdz> i'm probably missing something obvious
<Bitweasil> I think Haswell is 4th and 5th?
<Bitweasil> But the tasks are compute, so I don't care about no hyperthreading.
<gog> dzwdz: the selector is the upper 13 bits of the segment register, so shift that right by 3 and you get 5
<gog> or is it 14 bits
<gog> 13 bits yeah
<gog> s/selector/index/
<gog> it's conveniently the same as the offset into the table
<gog> unless your RPL is different
<Bitweasil> Er, wait. Hm.
<Bitweasil> Huh. My i7-6770HQ is apparently Skylake. Thought that box was Haswell.
<gog> wait yes 5xxx is 5th gen
<gog> cause i had a 5470
<gog> or was it 4750 lmao
<gog> i can't remember
<gog> some combination 4, 5, 7 and 0
<Bitweasil> I've got a 5775C too.
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<Bitweasil> That's maybe Skylake too?
<Bitweasil> Oh, Broadwell.
<Bitweasil> Whatever, cheap CPUs to crunch BOINC with.
<Bitweasil> mitigations=off and yolol.
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<dzwdz> sorry for yet another noobish question, but what should tss.esp0 be set to? the pointer to the top of the stack?
<dzwdz> the wiki pages about tss are not that clear
<geist> top of the stack you want the SP to be set to when transitining from ring3 to ring 0
<geist> but... are you implementing user space yet? if not, dont worry about the TSS
<geist> if you're just getting protected mode working you can ignore all of that
<dzwdz> i want to get to userspace asap
<dzwdz> i want to implement most stuff in there
<moon-child> microkernel?
<dzwdz> kinda
<geist> okay
<Bitweasil> gog, for pure compute boxes, yup!
<Bitweasil> They literally don't do anything but BOINC.
<gog> i like to live dangerously so i turned them off so i could actually play what few games i can :
<gog> :p
<gog> wtf is with my p key
<geist> dzwdz: in that case the TSS stuff is all so that the cpu knows what SP to set when it transitions from ring3 to ring 0
<dzwdz> so it should be the top of the stack, right?
<dzwdz> so the syscall handler would be at the top
<geist> right
<geist> top of the *kernel* stack
<dzwdz> ok, thanks
<geist> since you'll want a separate stack in the kernel and user space, to separate their priviledge
<moon-child> also so if userspace does something funky with its stack, kernelspace won't be hurt
<geist> it's basically some dumb leftover residual thing from the far more complicated hardware task switching that you can't/shouldn't use anymore
<moon-child> (well, I guess that is priviledge separation)
<geist> really all you need is a MSR to set the RSP0 to switch to, but it's legacy
<dzwdz> isn't everything in x86 dumb leftover residual stuff
<geist> basically
<geist> though it'll just be confusing now, i do recommend reading intel FRED whitepaper
<dzwdz> i considered going with arm but the docs that i could find were kinda shitty
<geist> it's a proposal that intel has to greatly simplify this stuff
<dzwdz> i couldn't even find how to read stuff from the microsd on the rpi
<geist> if you want ust pure simple: riscv
<dzwdz> risc-v is that cool open source one, right?
<geist> but also suggest starting on qemu first, and it'll also emulate pretty much anything
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<kazinsal> the intel FRED stuff looks pretty cool with the obvious downside of it not being able to be greenfielded for quite a while
<kazinsal> but perhaps in 10 years we'll finally be free of all the existing weird mode transition bits
<gog> same :|
<moon-child> the worst part is amd has their own thing
<moon-child> so it's not like we can just switch to fred and forget everything that came before
<kazinsal> yeah, the AMD one looks like it's meant more for retrofitting
<kazinsal> whereas FRED is great for a clean slate design
<dzwdz> a clean slate design for something on x86 sounds like a bad idea
<travisg> i dont like that it goes more all in on dumping *more* state on the stack, but iirc it has a fairly clean way to deal with double fault/triple faults
<travisg> so it's not terrible
<dzwdz> unless you're throwing the entire arch away
<travisg> from my recent fiddling with 68k, it actually looks much closer to that
<travisg> with the exception that it uses even less vectors. but the notion of dumping a large amount of state that pretty much fully describes whats going on (like cr2, etc) directly in a frame such that it's 'atomic' is nice
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<dzwdz> how can i check if i've set up the GDT correctly?
<dzwdz> if it doesn't crash it's fine, right?
<moon-child> lgdt, set segregs, and do some memory accesses
<moon-child> not you can't load cs directly; you have to do a far jmp/call/ret
<dzwdz> i'm calling a bunch of functions which access the vga memory and it works
<dzwdz> i'm not sure what you mean by setting segregs though
<dzwdz> wait, if i don't have paging yet i could iret into ring3 and try accessing the vga memory directly, right?
<dzwdz> and if that works then it means that everything is correct
<moon-child> so say segment #1 is your data segment. You need to mov ax, 8 mov ds, ax
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* gog meows
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* moon-child pets god
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