<geist>
soooo. okay, yeah i get it, that's kinda dangerous, but get off my back i know what i'm doing
<gog>
nanny compiler
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<doug16k>
why does it think it is 0, 0 ?
<clever>
doug16k: i think `void*` is considered an array of zero length?
<geist>
doug16k: i dont know where it's supposed to get the length from in this case
<geist>
well shoving it through a unsigned char doesn't really help
<geist>
it still thinks it's a region of size 0
<doug16k>
it wants (char(*)[1024]) then?
<geist>
i dunno! i haven't figured out how to stop it
<klange>
< clever> my rough understanding of AA, is to just render at 2x the normal res then blend each 2x2 pixel block back down to 1 pixel, is that right? ← In this case, I'm taking a very different approach than subsampling; with simple edge polygons you can know exactly where they cross a given scanline and use that to get much better values
<klange>
this seems to be the typical approach for font glyphs
<geist>
huh the #pragma GCC diagnostic stuff doesn't even stop this
<geist>
ugh.
<doug16k>
I'd cast it to an array that size
<geist>
i can kill it at the module level by turning off the warning but this is annoying
<doug16k>
it's probably __attribute__((__access__((__write_only__, 1, 3))) on memset doing it
<geist>
yah going through a pointer doesn't silence it either
<geist>
it's part of some new feature in 11 i think that's trying to dynamically track the size of things you're pointing at
<doug16k>
cast to array you mean
<doug16k>
is it easy to repro in godbolt?
<geist>
yah i cast it to a 'unsigned char (*foo)[1024] = myptr;' and then memset that
<geist>
same thing
<doug16k>
microsoft compiler has been doing that for about 15 years now
<doug16k>
mostly for security
<doug16k>
their code is full of ugly macros that annotate every buffer bounds
<kingoffrance>
"compiler pulls shit" -> "talk to the pragma" lol
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<doug16k>
I just hit the code analyzer over the head with something I am allowed to do because the language is designed to maximize memory corruption
<moon-child>
haha
<doug16k>
could it be argued that your define is wrong, and it should be BUFFER = 0x1000; in your linker script, and the code should say char BUFFER[] ?
<doug16k>
er, extern *
<doug16k>
you could make one of your source files a linker script, with just this line: BUFFER = 0x1000;
<doug16k>
and treat it like an object file
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<doug16k>
I think BUFFER = ABSOLUTE(0x1000); will make it not generate relocations for it
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<doug16k>
hardcoded addresses belong in the link, don't you think?
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<doug16k>
hmm I guess that could cause problems with reach
<moon-child>
imo hardcoded addresses belong near the code that uses them. Otherwise it's kinda opaque
<doug16k>
the more I learn about toolchains, the more I am annoyed with them
<klange>
write your own
<moon-child>
I wrote most of an assembler, probably do linker next
<moon-child>
also most of a compiler. But register allocation and instruction selection are a pita
<klange>
I have most of a linker, and do plan to eventually write a C compiler similar to some of the other minimalist ones out there...
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<moon-child>
ye my mistake with the compiler was trying to go fancy. Have all this ssa and now you _have_ to do register allocation or it turns into kilobytes of stack space for a 5 line function
<moon-child>
I did it the second way, does not work
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<geist>
doug16k: interesting
<geist>
moon-child: for soem reason that pragma thing doesn't work here
<geist>
sadly it's actually more complicated in my code base, the BUFFER #define is machine/platform specific, etc
<geist>
so it's harder to do
<moon-child>
at the call site, not the definition. Like nowarn(memset(...))
<bslsk05>
www.vunetfinland.com: Russian Market News | Virtualization Information Technology Start Up JTMOS Is Looking For Investors, Expanding To Russia And China - Bid Today!
<Izem>
good luck
<doug16k>
interesting. 11263 fps to render 3 white triangles into 640x480 window
<klange>
yeah, just need to actually draw something real with it instead of messing around with with a mouse
<doug16k>
you need to render polygons with some segments being bezier curves, right?
<klange>
A typical approach is to tesselate the curves to lines by calculating midpoints and comparing to the midpoint of a line segment, tesselating until a threshold - half a pixel or so.
<doug16k>
ah
<klange>
But I think I'll start doing some ttf parsing first and see where that takes me...
<klange>
thinking of calling this library the toaru truetype text transformer
<klange>
or ttttt
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<FireFly>
or t5 for short? :p
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<doug16k>
klange, you could add the word "tiny" and add another t
<doug16k>
toaru tiny truetype text transformer
<moon-child>
also do true type as two separate words
<moon-child>
then you get 7 ts
<doug16k>
I'm guessing your implementation will be surprisingly low line count
<GeDaMo>
If will if you put all the code on one line :P
<klange>
truetype was already two separate words Toaru TrueType Text Transformer = TTTTT
<moon-child>
oh, then add 'the' to the beginning
<GeDaMo>
Tremendous! :P
<moon-child>
tremendous and tiny? Sounds a bit oxymoronic :)
<GeDaMo>
Tremendously tiny :P
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<klange>
Well, I did next to nothing with this today... just cleaned up what I already had, hopefully optimized it a bit, made sure it worked with colors and alpha blending...
<klange>
... in theory.
<klange>
But I'm sure it'll occupy my evenings for the next few days. And probably my lunches.
<sortie>
Today I merged the ATAPI support I did three years ago
<klange>
I should probably at least get my old ATA/ATAPI drivers ported to Misaka since they're not too complicated...
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<ZetItUp>
yeah the time was pretty hard, borrowed alot of code :P
<ZetItUp>
and cheated with the shutdown since it's running in qemu
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<NieDzejkob>
is there a way to make use of BIOS disk access through trips back to real mode if I'm running in long mode?
<clever>
NieDzejkob: i think win95 was doing just that, it could basically do a soft-reboot to get back into real real mode, restore some state, call the bios routine, then go back into paged mode
<clever>
and thats why realmode drivers sucked, and it was recommended to get proper paging capable drivers
<gog>
you could do PIO
<gog>
unless there's a specific need to use the BIOS service
<NieDzejkob>
well I'm using USB, I don't think there's an equivalent of PIO for that :D
<gog>
ah yes that's fair lol
<NieDzejkob>
clever: I don't think win95 was using long mode :P
<clever>
yeah, it was using a 32bit protected mode
<gog>
windows 95 x64 edition
<clever>
in that case, you would have to tell the bios to stop doing usb/ata emulation, and then run your own usb drivers
<clever>
and there at least 4 different usb drivers you have to deal with
<clever>
ehci, ohci, xhci, and i forget
<NieDzejkob>
usb/ata emulation is a thing? as in SMM port mitming emulation?
<clever>
NieDzejkob: its done via the bios disk read api
<clever>
so as long as you ask the bios to read the internal hdd, it can fake a drive being internal
<clever>
ipxe can also hijack those routines, and make a network block device appear internal
<NieDzejkob>
and there's no way to go long mode -> protected mode -> real mode -> protected mode -> long mode?
<doug16k>
sure you can
<NieDzejkob>
not expecting great performance or anything, just as a stopgap
<clever>
i had heard that dropping back to realmode wasnt really possible, you could only hit the main cpu reset line
<doug16k>
clever, wrong
<doug16k>
on 80286
<clever>
and then leave an entry point somewhere in ram, for the bios to return control to you
<clever>
doug16k: ahh, a lot of these things ive heard, have long been fixed then
<NieDzejkob>
it requires >=386 IIRC but tbh idgaf
<doug16k>
yeah, intel thought protected mode was so good, you'd stay in it forever, and thought it would be really secure to make it stuck in pmode
<doug16k>
the idiot 80286 team
<clever>
and then the 386 team fixed that?
<doug16k>
yes
<clever>
i can kinda see similar choices done on arm, but better, with EL2/EL1
<doug16k>
LMSW instruction can't clear PE
<doug16k>
mov to CR0 can
<clever>
once in EL1, your basically stuck, and can only regain EL2 if the code in EL2 co-operates
<doug16k>
NieDzejkob, all you need to do on top of the pm->rm->pm is make the long mode code far jump to a code segment that has L=0, D=1, then turn off paging, then turn off LME, now you are in protected mode
<j`ey>
clever: just do a HVC, then youre in EL2 :P
<NieDzejkob>
what about interrupt setup?
<NieDzejkob>
do BIOSes usually make assumptions about that?
<NieDzejkob>
wrt. disk access
<clever>
j`ey: but if EL2 isnt co-operating, you cant do anything useful via HVC, so it can lock you in EL1, or treat HVC as fatal
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<doug16k>
you know what is the most funny about the inability of 80286 to get out of protected mode? IBM foolishly added hardware to the motherboard to make the keyboard controller able to reset the cpu
<j`ey>
clever: :)
<doug16k>
this is all they needed: mov $ 1,%sp ; push $ 1
<doug16k>
^ resets cpu
<NieDzejkob>
uhhhh what
<doug16k>
triple fault
<doug16k>
even works in real mode
<NieDzejkob>
hah, do faults happen in real mode too?
<clever>
doug16k: i heard something about the original xbox cpu, was changed at one point in the design, and that impacted how it behaved in tripple-fault cases
<NieDzejkob>
but stack pointer rolling over includes those?
<doug16k>
and there is an into instruction to raise that. and eflags.TF exists, and 0xcc breakpoint opcode
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<doug16k>
NieDzejkob, stack pointer can't wrap since 80286
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<NieDzejkob>
and it raises a stack fault instead?
<doug16k>
it's a stack fault. it tries to push the frame. that causes double fault, that can't push, resets
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<doug16k>
only in protected mode is it possible to escape the reset
<doug16k>
in protected mode, the cpu interprets the IDT completely differently. in that case, a task gate could make it switch to a new stack
<doug16k>
in real mode, it isn't possible to prevent the triple fault
<NieDzejkob>
are task gates typically used for interrupt handling, then, or do you just use the ESP0 in TSS?
<doug16k>
PE does two things: changes the meaning of loading a value into a segment register, changes the format of the IDT entries
<doug16k>
that's about it
<NieDzejkob>
also, what's the point of LMSW if mov to cr0 exists? was the latter added in 386 or something?
<doug16k>
the task gate solves it because it will save the nonsensical ss:sp to the main TSS, and switch to the ss:sp in the other task
<doug16k>
yeah, lmsw was the way to enable pmode on 286. 386 added control registers, and made cr0 take over what lmsw did
<doug16k>
lmsw still works, but it still won't let you clear PE with it
<NieDzejkob>
compatibility I guess :P
<NieDzejkob>
someone may've tried setting the other bits with a word that has PE=0
<doug16k>
yeah, some code might rely on exceptions to occur. they expect and rely on it
<doug16k>
lmsw = load machine status word
<NieDzejkob>
yeah, looked that up already. though I initially confused it with wrmsr
<doug16k>
286 was how the idt and gdt entries ended up in the mess layout they are in now
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<doug16k>
it was as if the 286 team expected to just toss the whole thing on 32 bit cpu
<NieDzejkob>
oh I only now realized that 286 was the one with 16-bit PM
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<doug16k>
yes. 64K limit max
<NieDzejkob>
does the SDM document what was added when?
<doug16k>
not really
<doug16k>
I think the idea is, you get the manual for the year you want to support back to, and they guarantee everyting still works forever :P
<doug16k>
a 286 OS would work fine on my 3950x
<doug16k>
I want to run OS/2 on bare hardware just for a laugh someday
<doug16k>
it's amazing for that to still work, giving how crazy aggressive modern x86 out-of-order is
<doug16k>
imagine the instruction fetch bandwidth, getting 32 bytes per clock or more
<doug16k>
cache hit staying perfectly at 100% forever because it hardly even needs the L2
<doug16k>
I am amused by running really old software on extremely fast hardware, at a speed that the original programmers would think to be impossible
<doug16k>
imagine the speed of a foxpro 2.6 query or UI update on a smartdrv 64M? probably not even one scanline of monitor scanout of delay
<doug16k>
the code had to run like lightning to be good at the time
<doug16k>
on a 33MHz 486, foxpro was instantaneous speed. imagine 4300MHz massively out of order with gigantic caches and crazy ram clock
<doug16k>
why is all code so ridiculously slow now?
<doug16k>
I'm guilty of it
<doug16k>
my bootloader is all nice guy and reads the program headers and allows the content to be strewn all over the place
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<doug16k>
what really should be happening is, there is a memory image that is just flat contiguously stored on disk and I just single-DMA-transfer the entire "kernel load" and jump into it instantly
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<doug16k>
when I picture slapping the image on disk and requiring contiguous and the kernel being a bin image, I imaging those as bad things. those things make it ludicrous speed
<doug16k>
it's like we're brainwashed that the slow thing is great and the instant thing is cheesy
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<doug16k>
I am being asked to speed up python database code on AWS
<doug16k>
I wish AWS was as fast as the 486DX-100 I had in the '90s
<doug16k>
it's not even close
<doug16k>
I guess if you stack up enough cold start delays, you can make any machine slower than a 486 in DOS with dbase B+ ISAM
<doug16k>
why get one cpu to cache credentials once and reuse them million times, when you can get database credentials by making it do a request to a vm (that is likely off) every time
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<doug16k>
it's physics. they make more money if it wastes cpu, so there is a force pushing it to waste more cpu
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<vai>
hi
<vai>
Its pretty commond you do page tables in a static memory area, physically and virtually mapped alike ?
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<vai>
page directories e.g.
<doug16k>
vai, yeah. even if you made it more elaborate, you might do that at first, and transition to the fancy one
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<vai>
user and kernel page directories are seperate spaces to avoid conflicts
<vai>
also global seperate
<vai>
doug16k: oh yeah
<clever>
vai: on arm32, there is a configurable split between the upper and lower chunk of the virtual space, and each has its own paging table
<vai>
doug16k: first 4 megabytes or so is kernel code/data area for all that I mentioned + more
<vai>
clever: I/O memory mapped areas same as in IA-32 ?
<clever>
i think the config was just the number of bits that must all be 1 for an upper addr
<vai>
0xc000 0000 or so
<clever>
vai: i dont know x86 paging that well
<vai>
physically
<doug16k>
the stuff below 1MB is all the same as usual yeah
<vai>
clever: ARM PCs = still PCs? I think? :-)
<doug16k>
ah only talking to clever. I'll stop interrupting
<doug16k>
I thought you meant long mode vs 32 bit vm machine
<doug16k>
you can expect I/O windows above 2GB
<doug16k>
the closer you get to 4GB line, the more unlikely it is ram there
<doug16k>
usually from 4GB up is all ram
<doug16k>
but you need to use whatever memory map you get on that platform
<doug16k>
so you don't really care to know where ram is or isn't, it's dynamic
<doug16k>
my bootloader could handle every other page not being ram
<doug16k>
starting at 1M line
<j`ey>
lol
<j`ey>
that would be an interesting machine
<doug16k>
yes lol
<doug16k>
I think bcos said his is that pessimistic too
<j`ey>
but you couldnt dma with more than 1 page then D:
<doug16k>
yes, it would be awful
<doug16k>
it works because the whole kernel image expects to be at the vaddr completely ready to go, at entry
<doug16k>
entry point is at fffffff....
<doug16k>
it already had to use paging for the whole loading process
<doug16k>
had to prepare the page tables I mean
<kc8apf>
that's kinda how memory layout looks on TrustZone-M. They use a bit in the physical address to determine secure vs non-secure. SRAMs and many other devices have aliases to both so you end up with alternating blocks of secure and non-secure.
<doug16k>
no problem making it handle gaps
<doug16k>
x86 has that for SMM memory
<kc8apf>
SMM at least takes a single range
<doug16k>
there is an MTRR that strictly enforces that a certain physaddr range is inaccessible
<kc8apf>
This is bit 23 or something
<doug16k>
that reminds me that I should be working on my qemu patch
<doug16k>
(I extended info tlb to show the memory type, considering the PTE bits, PAT, and MTRRs, and the priority rules in the SDM)
<doug16k>
tells you resulting memory type, the PTE memory type (from PAT lookup) and the MTRR type
<doug16k>
and yells about UB combinations
<doug16k>
and UB overlaps
<doug16k>
that's all done. I want to also extend it to be like a hex dump, where it omits contiguous regions if they all have the same type bits
<doug16k>
klange suggestion
<klange>
only the best ideas from me, of course
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<doug16k>
I always expand my patches to the point where they are uneasy with the size of the patch :D
<klange>
my thinkpad has been booted into toaruos for four days now and I keep refreshing the weather panel widget and I'm almost surprised it keeps working
<doug16k>
the gdbstub fix one was pretty funny. I drastically changed the machine description xml and they had no idea why (gdb was rejecting it silently)
<doug16k>
was using builtin description and broke any time gdb asked for orig_eax
<doug16k>
so register window was broken completely in a gui debugger
<doug16k>
orig_eax is part of linux syscall abi
<doug16k>
screwy in TUI too
<doug16k>
layout regs showed empty pane
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