10:20 <Guest97> Hello, I'm new to openocd and had question. I want connect / load image to a TI SoC (IWR1843). It has an Arm core (R4) and a DSP core (C674x). When I connect with openocd I see only a single TAP. Is this correct even for my dual core chip?

10:22 <Guest97> I'm using XDS110 debugger

10:46 <PaulFertser> Guest27: Hi!

10:47 <PaulFertser> Guest27: TI SoCs usually have a "JTAG router" which needs special handling. You can see examples of dealing with "icepeak" in the existing target files.

10:52 <Guest27> Hi Paul. Yes, I came across IcePick. Apparently the SoC has an IcePick_M. I wondered if this is what I see as my TAP (because apparently this is a "primary" TAP and all other modules are "secondary"). So I was studying this file and others:

10:52 <Guest27> https://github.com/arduino/OpenOCD/blob/master/tcl/target/ti_dm6446.cfg

10:52 <Guest27> but I did not understand why the taps are declared as such (eg. first tap declared type "unknown")

10:52 <Guest27> So I didn't know how to modify this for my SoC - seems beyond my knowledge at the moment.

10:53 <PaulFertser> Guest27: yes, most probably the only tap you see is the icpick tap which expects you to use special commands to connect other taps to the chain. They need to be declared too in config but with -disable option.

10:55 <PaulFertser> The datasheet should tell which JRC tap number is what additional tap.