00:08 <mwette> I'm seeing that the microchip softconsole tool uses openocd. I hope they upstream the updates.

01:50 <karlp> don't we all :)

07:28 <IanH> Hello, I am trying to connect to a target that has a coresight SoC-600 configuration without an AP between the DAP and the core's debug registers. When attempting to connect to the target, OpenOCD verbose debug (-d4) show it tries to access AP registers such as CSW and TAR which do not exist with this coresight configuration. The core's debug

07:28 <IanH> registers are accessible via an apbic connected to the DAP. So they can be accessed similarly to the root ROM table. Do you know whether such a coresight configuration is supported? Any ideas are much appreciated

08:34 <PaulFertser> IanH: hi! This is quite an unusual configuration. Probably "memap" target can work?

09:15 <borneoa___> IanH: soc-600 should adiv6. OpenOCD is unable to auto detect adiv5 vs adiv6 and the default is adiv5. You need a specific flag at DAP create to specify it is adiv6

09:21 <borneoa___> IanH: soc-600 should "be" adiv6.... It's always hard to write from a phone!

09:25 <PaulFertser> And ADIv6 doesn't have an AP?

10:10 <IanH> Thanks a lot both :) I use -adiv6 when creating the dap, and "dap info" successfully displays the ROM table. Thanks for the hint with mem_ap. I took a look at mem_ap.c source. It may well work better to establish the initial connection if it does not try to access an AP, and I will try this when I next get on the hardware. However it is clear I

10:10 <IanH> will not be able to debug using mem_ap as it emulates a core from gdb's perspective.

10:13 <PaulFertser> IanH: your setup seems to be really custom/uncommon, sorry for not giving any direct advice, apparently you already know enough about ADI to make a fair judgement after reading a bit through the OpenOCD sources.

10:14 <borneoa___> PaulFertser: yes, it has an AP but the way to handle the access through the registers in DP is different.

10:14 <PaulFertser> I wonder how it's supposed to work even, without an AP, and why, and whether it's allowed per Coresight specs.

10:17 <borneoa___> IanH: the target mem_ap is NOT a real target that you can use with GDB for debug. It is a virtual target to allow read/write in the bus behind the AP.

10:18 <borneoa___> IanH: some IDE use a dedicated GDB connection to inspect the memory behind the AP, they name it "live variables view". The target mem_ap can be used for this purpose too

10:26 <IanH> Thank you for the advice you could give. Even knowing that it is an unusual setup is helpful information. My device includes an AXI-AP for accessing memories so the mem_ap will be useful for that. Based on what I now know, I suspect I need to modify source to get this to work with a debugger. Regarding how it is supposed to work: using hand-crafted

10:26 <IanH> JTAG I can access the core debug registers and CTI registers that would typically be used during debugging. A read of a debug register is achieved the same way as a read of an ROM table entry, just with a different address.

10:31 <IanH> Regarding whether it is allowed per Coresight specs. I am not sure. Figure A1-1 on page 24 of the Arm Debug Interface Architecture Spec https://developer.arm.com/documentation/ihi0074/latest/ shows coresight components that are not behind any AP and this seems in-line with the setup I have. In any case I wish the chip designers had put the

10:31 <IanH> coresight components behind an AP!

10:34 <borneoa___> IanH: what is the soc and what CPUs it has?

10:35 <borneoa___> IanH: mem_ap is just a tool to access memory, not for debug

10:38 <borneoa___> IanH: there are soc that after reset open only one dedicated AP to start the debug authentication though some memory mapped register. When the debugger sends the correct password or certificate, then the boot-rom opens the other AP's for the CPU debug. Arm calls it ADAP. Is this the case on your system?

11:09 <IanH> It is a custom ASIC with a Cortex-R52. ADAP or a similar mechanism is not used as far as I know, but I'll ask the designers just in case.

11:20 <borneoa___> IanH: the ROM table dumped with 'dap info' shows the debug block of CR52? In that case you can simply define the target 'aarch64' on that AP. Check from other config files that declare aarch64 targets