#nmigen on 2021-11-22 — irc logs at libera.irclog.whitequark.org

2021-05-19 21:39 whitequark changed the topic of #nmigen to: nMigen hardware description language · code https://github.com/nmigen · logs https://libera.irclog.whitequark.org/nmigen

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01:44 <cr1901> .oO (Is the nmigen rebranding going to be cat-themed?)

01:44 <whitequark> no

01:44 <cr1901> Well, there goes my one good guess

01:51 <d1b2> <TheManiacalLemon> Yosyshq already called dibs on the cat theming ;)

01:51 <whitequark> yeah

01:52 <cr1901> That's exactly why I thought nmigen would use it

02:03 <whitequark> I think it makes a lot of sense to differentiate this language from the Yosys project

02:04 <whitequark> both are a part of the general OSS HDL toolchain space but the projects are distinct, even if they depend on each other to some degree

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10:36 <_whitenotifier-b> [nmigen] mattvenn opened issue #647: Download link is wrong on https://nmigen.info/nmigen/latest/start.html - https://git.io/J1dr6

10:42 <_whitenotifier-b> [nmigen] mattvenn commented on issue #637: `sim` submodule is missing after `pip install --upgrade nmigen[builtin-yosys]` - https://git.io/J1dKn

10:45 <_whitenotifier-b> [nmigen] mattvenn commented on issue #637: `sim` submodule is missing after `pip install --upgrade nmigen[builtin-yosys]` - https://git.io/J1d6U

11:01 <_whitenotifier-b> [nmigen] whitequark commented on issue #647: Download link is wrong on https://nmigen.info/nmigen/latest/start.html - https://git.io/J1dX2

11:04 <_whitenotifier-b> [nmigen] whitequark commented on issue #637: `sim` submodule is missing after `pip install --upgrade nmigen[builtin-yosys]` - https://git.io/J1d1s

11:17 <_whitenotifier-b> [nmigen] chipmuenk closed issue #637: `sim` submodule is missing after `pip install --upgrade nmigen[builtin-yosys]` - https://git.io/Jgeuz

11:17 <_whitenotifier-b> [nmigen] chipmuenk commented on issue #637: `sim` submodule is missing after `pip install --upgrade nmigen[builtin-yosys]` - https://git.io/J1dyB

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