#nmigen on 2021-11-08 — irc logs at libera.irclog.whitequark.org

2021-05-19 21:39 whitequark changed the topic of #nmigen to: nMigen hardware description language · code https://github.com/nmigen · logs https://libera.irclog.whitequark.org/nmigen

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00:21 <_whitenotifier-1> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JXBtk

00:21 <_whitenotifier-1> [YoWASP/nextpnr] whitequark 0a31e10 - Update dependencies.

00:56 <_whitenotifier-1> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JXBlB

00:56 <_whitenotifier-1> [YoWASP/yosys] whitequark b0ec887 - Update dependencies.

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13:36 <FL4SHK> whitequark: so I just tested it, and there appear to be no latches in the code I've written

13:37 <whitequark> yeah, that's the expected outcome

13:37 <whitequark> any reason you -are- expecting latches?

13:37 <FL4SHK> based upon the generated Verilog, there was a case statement that was not fully filled out

13:38 <whitequark> oh, I see

13:38 <whitequark> could you show me the code?

13:38 <FL4SHK> The Verilog or the nMigen code?

13:38 <whitequark> Verilog

13:39 <FL4SHK> https://paste.ee/p/9BPI4

13:39 <FL4SHK> for example, see `\outp_d2h_data_1$next`

13:42 <whitequark> oh!

13:42 <whitequark> so the line 162 guarantees that there won't be a latch inferred

13:43 <whitequark> there will always be such a line because of how the RTLIL backend works

13:43 <whitequark> regardless of the code you write

13:49 <FL4SHK> ah

13:49 <FL4SHK> thanks

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