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<
_whitenotifier-1>
[YoWASP/nextpnr] whitequark 0a31e10 - Update dependencies.
<
_whitenotifier-1>
[YoWASP/yosys] whitequark b0ec887 - Update dependencies.
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FL4SHK>
whitequark: so I just tested it, and there appear to be no latches in the code I've written
<
whitequark>
yeah, that's the expected outcome
<
whitequark>
any reason you -are- expecting latches?
<
FL4SHK>
based upon the generated Verilog, there was a case statement that was not fully filled out
<
whitequark>
oh, I see
<
whitequark>
could you show me the code?
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FL4SHK>
The Verilog or the nMigen code?
<
whitequark>
Verilog
<
FL4SHK>
for example, see `\outp_d2h_data_1$next`
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whitequark>
so the line 162 guarantees that there won't be a latch inferred
<
whitequark>
there will always be such a line because of how the RTLIL backend works
<
whitequark>
regardless of the code you write
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