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[nmigen-boards] hansfbaier synchronize pull request #154: Add support for QMTech Boards EP4CE15, EP4CE55, 5CEFA2, 10CL006 and XC7A35 and their common daughterboard - https://git.io/JGvXe
<_whitenotifier-1>
[nmigen-boards] hansfbaier synchronize pull request #154: Add support for QMTech Boards EP4CE15, EP4CE55, 5CEFA2, 10CL006 and XC7A35 and their common daughterboard - https://git.io/JGvXe
<_whitenotifier-1>
[nmigen-boards] hansfbaier synchronize pull request #154: Add support for QMTech Boards EP4CE15, EP4CE55, 5CEFA2, 10CL006 and XC7A35 and their common daughterboard - https://git.io/JGvXe
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[nmigen-boards] hansfbaier edited pull request #154: Add support for QMTech Boards EP4CE15, EP4CE55, 5CEFA2, 10CL006 and XC7A35T and their common daughterboard - https://git.io/JGvXe
<_whitenotifier-1>
[nmigen-boards] hansfbaier synchronize pull request #154: Add support for QMTech Boards EP4CE15, EP4CE55, 5CEFA2, 10CL006 and XC7A35T and their common daughterboard - https://git.io/JGvXe
<_whitenotifier-1>
[nmigen-boards] hansfbaier commented on pull request #154: Add support for QMTech Boards EP4CE15, EP4CE55, 5CEFA2, 10CL006 and XC7A35T and their common daughterboard - https://git.io/JPNl3
<_whitenotifier-1>
[nmigen-boards] hansfbaier commented on pull request #154: Add support for QMTech Boards EP4CE15, EP4CE55, 5CEFA2, 10CL006 and XC7A35T and their common daughterboard - https://git.io/JPN4a
<_whitenotifier-1>
[nmigen-boards] hansfbaier synchronize pull request #154: Add support for QMTech Boards EP4CE15, EP4CE55, 5CEFA2, 10CL006 and XC7A35T and their common daughterboard - https://git.io/JGvXe
<_whitenotifier-1>
[nmigen-boards] hansfbaier commented on pull request #154: Add support for QMTech Boards EP4CE15, EP4CE55, 5CEFA2, 10CL006 and XC7A35T and their common daughterboard - https://git.io/JPN45
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<FL4SHK>
whitequark: any thoughts on arrays of interfaces like in SV?
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[YoWASP/yosys] whitequark pushed 3 commits to release [+0/-0/±3] https://git.io/JPxu2
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[YoWASP/yosys] whitequark 4ae03d9 - Allow using any absolute or relative paths on Linux and Windows.
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[YoWASP/yosys] whitequark 33f7191 - Use upstream YOSYS_VER variable verbatim when computing version.
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[YoWASP/yosys] whitequark 5b8037b - Prepend YoWASP Python module path to `sys.path`, not append.
<whitequark>
FL4SHK: in the scheme I described earlier, interfaces aren't nmigen `Value`s, they're mostly normal Python objects
<whitequark>
which means you can just have an array of them like you can have an array of anything else
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[nmigen/nmigen] whitequark pushed 1 commit to master [+1/-0/±0] https://git.io/JPxos
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[nmigen/nmigen] whitequark a2ef4cb - Add PEP 518 `pyproject.toml`.
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[nmigen/nmigen-boards] whitequark pushed 1 commit to master [+1/-0/±0] https://git.io/JPxo8
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[nmigen/nmigen-boards] whitequark bd7fdd3 - Add PEP 518 `pyproject.toml`.
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[nmigen/nmigen-stdio] whitequark pushed 1 commit to master [+1/-0/±0] https://git.io/JPxoE
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[nmigen/nmigen-stdio] whitequark 9e222b9 - Add PEP 518 `pyproject.toml`.
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[nmigen/nmigen-soc] whitequark pushed 1 commit to master [+1/-0/±0] https://git.io/JPxoa
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[nmigen/nmigen-soc] whitequark d0e6c70 - Add PEP 518 `pyproject.toml`.
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[nmigen/nmigen-yosys] whitequark pushed 2 commits to develop [+1/-0/±2] https://git.io/JPx6n
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[nmigen] cr1901 edited a comment on issue #505: Formal Platform Integration - https://git.io/JPpvI
<Sarayan>
what is the kind of things one can prove in HDLs nowadays?
<cr1901>
I mainly use it lately for equivalence checking. B/c "instead of trying a specific input stimulus via simulation, why not try _all_ of them :)?"
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<Sarayan>
you prove if the "circuit" is equivalent to math/software?
<vup>
its also been really useful for anuejn and me to check things like stream contracts (the two way handshake stuff), because somehow we managed to fuck them up a lot :)
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[YoWASP/nextpnr] whitequark pushed 12 commits to release [+0/-0/±12] https://git.io/JPpOO
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[nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JPp0s
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[nmigen/nmigen] whitequark 03eed8d - Deploying to gh-pages from @ 0b28a97ca00b44301fb35e2426d571e4f6640040 🚀
<tpw_rules>
whitequark: you mentioned offhandedly a bit ago that there was a rebranding in the pipeline. is there any timeline on this? i am just curious