<DeVosReynaerde>
When using the build-in memory modules from nMigen, is it possible to use byte-addressing when having a word length of 32 bits i.e. a way to concatenate the next 3 bytes within the same clockcycle?
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<d1b2>
<TheManiacalLemon> dual port RAM with some comb logic to reassemble the three bytes?
<DeVosReynaerde>
Thanks for the suggestion! In the mean time, we resolved it by using a memory width of 32 bits and just right shifting the byteadress twice.
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<d1b2>
<TheManiacalLemon> I remember long time ago struggling with an 8051 core that wanted 3 bytes of memory read at once... problem is, it needed to be overlaid so address 1 was bytes 1 2 3, address 2 was bytes 2 3 4
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<d1b2>
<TheManiacalLemon> only recently realized as I got back into FPGA stuff that I could do it with two 16-bit ROMs and just overlay them accordingly. The biggest issue was realizing that no matter how I sliced it, I'd have to deal with the potential of a dual read
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<_whitenotifier-1>
[nmigen] JarrettBillingsley commented on issue #291: Need a way to attach attributes to memories - https://git.io/J1TGX
<d1b2>
<wgoldie> does anyone know of an example of using (all of) the icebreaker spi memory in nmigen? i've done some code searching on github but no dice so far.
<d1b2>
<wgoldie> i can probably figure it out from scratch but it will presumably take a while 🙂