00:57 <_whitenotifier-1> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/J1ERL

00:57 <_whitenotifier-1> [YoWASP/yosys] whitequark 28bb330 - Update dependencies.

10:53 <kaucasus> Hey folks, I'm having an overflow error when trying to generate verilog for a platform. The core simulates fine. We've narrowed down the problem to it creating a very big wire in an ALU block that has shift operations.

10:53 <kaucasus> So somehow this code: https://pastebin.com/ycxfs5H6 generates a 4294967327 bit wide register, which of course is impossible to synthesise but isn't a problem for simulation, and is so big Python throws an overflow error

11:02 <kaucasus> oh derp, our bad, we shouldn't be able to shift with the full 32 bits width. It's just the lower 5 bits that are actually important (logically, since the databus is only 32 bits)

11:07 <whitequark> see https://nmigen.info/nmigen/latest/lang.html#lang-hugeshift

11:08 <kaucasus> Yeah it makes a ton of sense to do it that way, we also just read the spec wrong. We know do exactly as said in the note :P