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[YoWASP/nextpnr] ... and 8 more commits.
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[nmigen] hansfbaier opened issue #635: empty signal slice generates verilog which Quartus cannot parse - https://git.io/JzFJZ
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[nmigen] hansfbaier edited issue #635: empty signal slice generates verilog which can not be parsed by Quartus - https://git.io/JzFJZ
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[nmigen] hansfbaier edited issue #635: empty signal slice generates verilog which can not be parsed by Quartus - https://git.io/JzFJZ
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[nmigen] hansfbaier commented on issue #635: empty signal slice generates verilog which can not be parsed by Quartus - https://git.io/JzFU2
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[nmigen] andresmanelli commented on issue #554: Strange simulator behavior: clock signal pausing while sync blocks are speeding up - https://git.io/Jzpt1
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[nmigen] hansfbaier opened pull request #636: An attempt at fixing #635 - https://git.io/JzpZn
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[nmigen] hansfbaier synchronize pull request #636: An attempt at fixing #635 - https://git.io/JzpZn
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[nmigen] hansfbaier synchronize pull request #636: An attempt at fixing #635 - https://git.io/JzpZn
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[nmigen] hansfbaier synchronize pull request #636: An attempt at fixing #635 - https://git.io/JzpZn
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[nmigen] hansfbaier synchronize pull request #636: An attempt at fixing #635 - https://git.io/JzpZn