00:59 <_whitenotifier-d> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±2] https://git.io/Ju9n7

00:59 <_whitenotifier-d> [YoWASP/yosys] whitequark 6f67907 - Update dependencies.

01:30 <agg> yea, that would be great! especially if they could be somewhat fast and maybe had fpu...

01:56 <lethalbit> yeah a hard fpu would be nice too

04:39 <_whitenotifier-d> [nmigen-boards] antonblanchard opened pull request #183: orangecrab_r0_1: Fix program pin - https://git.io/JuHUn

07:05 <gatecat> I've noticed that Lattice are hiring SoC people for something like this, so it's probably 3-4 years away

07:06 <gatecat> idk if it will be RISC-V or ARM, either, but it's definitely the direction they are headed

07:36 <d1b2> <zyp> they're putting risc-v in other stuff like the mach-nx

08:11 <gatecat> the "hard block" in that is just a wirebonded crosslink nx die

08:11 <gatecat> (the user accessible fabric being an xo3d die)

16:12 <lkcl> lethalbit, dragonmux: nice!

16:14 <lkcl> any plans to add the ZC706? that's one i was donated in 2018 and haven't been able to use except with Vivado scripts

16:15 <lkcl> it's USD 2.5 THOUSAND and quite ridiculous that i can't use it with a Libre toolchain

16:15 <lethalbit> yeah, afaik the ZC706 is a PS7 block

16:15 <lethalbit> so it /should/ work afaik

16:16 <lethalbit> so once the ps7 block is working well then the platform file just needs to be made, can't do much about a fully vivado free flow atm tho

16:17 <lethalbit> i also kiiiinda got distracted thinking about how to possibly implement partial reconfiguration support into nmigen for the US+ chips >.>

16:17 <lkcl> coooool

16:17 <lkcl> :)

16:19 <lkcl> no heck as long as i can get, y'know... *something* working, i'll be delighted. i mean, it's a 350,000 LUT4s FPGA for goodness sake, easily capable of holding a Quad-Core SMP ASIC.

16:20 <lethalbit> well, assuming it really is a PS7 block then that /technically/ works now, even though it's not polished and one, dragonmux has done an amazing job

16:21 <lethalbit> if it's a PS8 block, uuh, still working on that >.>

16:24 <lethalbit> depending on how well my brain works this week/weekend i will /hopfully/ be able to work on the ps8 block and get it to synth

16:24 <lethalbit> also all of this involved me setting up a self-hosted github runner for vivado based CI which was /fun/ /s

19:33 <vup> why only partial reconfiguration for the US+ chips? the 7series ones also support it...

20:40 <lethalbit> i mean, eventually for all of the ones that support it

20:40 <lethalbit> but my current project that needs it is using a Zynq US+ MPSoC

20:41 <lethalbit> so i wannya get it working for that first, then work on the rest of the parts

20:41 <lethalbit> if that makes sense

21:03 <vup> sure, makes sense